Non-volatile look-up table for an FPGA

Details Non-volatile look-up table for an FPGA Non-volatile look-up table for an FPGA

2008-01-22

2008-01-22

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

C326S038000, C326S049000

Reexamination Certificate

active

11551973

ABSTRACT:
A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCCthrough a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.

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patent: 2003/0122578 (2003-07-01), Masui et al.
“Virtex-II Pro™ Platform FPGAs: Functional Description”, DS083-2 (v2.7) Advance Product Specification, Xilinix, Inc., pp. 25-26, Jun. 2, 2003.
“3.0 Look-Up Table—A Key Features Analysis (Configuration Logic Block—CLB) of the Xilinx Virtex II XC2V1000FG256AFT FPGA”, Report ID#: 1202-6218-PC51, TECHinsights, Semiconductor Insights, Inc., pp. 8-23, unknown date.
“Xilinx XCV300-4BG352CES”, Chipworks, pp. 1.0.0 CLB Block Diagram—2.2.3 LUT Data Input Selector Revision: 1.0, Jul. 7, 1999.

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