Non-volatile inverter latch

Details Non-volatile inverter latch Non-volatile inverter latch

1999-12-08

2000-11-07

Dinh, Son T.

Static information storage and retrieval

Floating gate

36518518, 36518527, G11C 1604

Patent

active

061445800

ABSTRACT:
A two-transistor, zero DC power, non-volatile inverter latch that can be made using floating-gate or SONOS technology to provide a consistent and/or reliable logic high and/or logic low output level. The inventive cell is useful for holding option settings in any custom integrated circuit or, more specifically, for holding configuration information (e.g., ASIC, PLD or FPGA interconnect data; configuration data for such ICs or for a clock/oscillator circuit or a microcontroller, etc.). The inventive cell outputs the data state immediately on power-up without any need for recall sequencing. The benefit of the invention comes from the potential for a very small cell which, in many applications, can substitute for non-volatile RAM.

REFERENCES:
patent: 4829203 (1989-05-01), Ashmore, Jr.
patent: 4885719 (1989-12-01), Brahmbhatt
patent: 5587603 (1996-12-01), Kowshik
patent: 5740106 (1998-04-01), Nazarian
patent: 5847993 (1998-12-01), Dejenfelt

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