Non-volatile DRAM cell

Details Non-volatile DRAM cell Non-volatile DRAM cell

1992-02-25

1994-07-19

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

H01L 2968, G11C 1124

Patent

active

053311884

ABSTRACT:
The present invention is directed to a one-transistor non-volatile DRAM cell having a two layer floating gate to allow the contents of a storage capacitor to be transferred to the floating gate during power interruptions. The first layer of the floating gate is separated from a storage node of the storage capacitor by a tunnel oxide to allow electron tunnelling between the floating gate and the storage capacitor. In another embodiment of the present invention, a dual electron injector structure is disposed between a one layer floating and the storage node to allow electrons to be injected between the floating gate and the storage node. In another embodiment of the present invention, an erase gate is implemented to remove the charge on the floating gate. The erase gate can be separated from the floating gate by a tunnel oxide or a single electron injector structure to allow electrons to travel from the floating gate to the erase gate.

REFERENCES:
patent: 4207615 (1980-06-01), Mar
patent: 4363110 (1982-12-01), Kalter et al.
patent: 4388704 (1983-06-01), Bertin et al.
patent: 4471471 (1984-09-01), DiMaria
Kalter, H. L., et al., "Dynamic Non-Volatile and Electrically Erasable Read-Only Memories", IBM Technical Disclosure Bulletin, 25(2):540 (Jul., 1982).
Kauffmann, B. A., et al., "Non-Volatile Dynamic Random-Access Memory Cell With Built-In Boosting", IBM Technical Disclosure Bulletin, 28(3):1182 (Aug. 1985).
Terada, Y., et al., "A New Architecture for the NVRAM-An EEPROM Backed-Up Dynamic RAM", IEEE J. of Solid-State Circuits,23(1):86 (1988).
Yasmauchi, Y., et al., "A Novel NVRAM Cell Technology for High Density Applications", IEDM, 416 (1988).

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