Non-volatile counter employing memory cell groups and fault dete

Details Non-volatile counter employing memory cell groups and fault dete Non-volatile counter employing memory cell groups and fault dete

1990-07-17

1992-04-14

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

377 241, 377 26, 371 102, 371 111, G06F 1100, H03K 2140

Patent

active

051054493

ABSTRACT:
A counter includes an array of memory cells arranged in groups of memory cells, each group designating a counting decade, wherein each group of memory cells includes first and second word strings, each capable of storing a data word, and a fault flag, capable of indicating which word string contains the data word; sensing means coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell; logic means coupled to the memory cells and to the sensing means for selecting the first or second word string in response to a fault signal; wherein upon detection of a fault in a first word string, the data word is written into the second word string; and a central shifting unit coupled to the memory array for reading a data word stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.

REFERENCES:
patent: 3331058 (1967-07-01), Perkins
patent: 4483001 (1984-11-01), Ryan
patent: 4566102 (1986-11-01), Hefner
patent: 4682287 (1987-07-01), Mizuno et al.
patent: 4727516 (1988-02-01), Yoshida et al.
patent: 4757522 (1988-07-01), Kieselstein
patent: 4774712 (1988-09-01), Lewis
patent: 4807264 (1989-02-01), Bauer
patent: 4947410 (1990-08-01), Lippmann et al.

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