Non volatile charge trapping dielectric memory cell...

Details Non volatile charge trapping dielectric memory cell... Non volatile charge trapping dielectric memory cell...

2005-06-07

2005-06-07

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S324000, C257S327000, C257S329000, C365S185260

Reexamination Certificate

active

06903407

ABSTRACT:
A dielectric memory cell comprises a substrate which includes a source region, a drain region, and a channel region positioned there between. A multilevel charge trapping dielectric is positioned on the surface of the substrate and a control gate is positioned on the surface of the dielectric and is positioned over and aligned with the channel region. The multilevel charge trapping dielectric includes a tunneling dielectric layer, a charge trapping dielectric layer, and a top dielectric layer. The tunneling dielectric layer comprises a first dielectric material having a wide band gap between a tunneling dielectric layer valance band Fermi level and a tunneling dielectric layer conduction band Fermi level. The top dielectric layer comprises a second dielectric material having a valance band Fermi level approximately equal to the tunneling dielectric layer valance band Fermi level and having a conduction band Fermi level greater than the tunneling dielectric layer conduction band Fermi level. The charge trapping layer is positioned between the bottom layer and the top layer of a third dielectric with charge trapping properties.

REFERENCES:
patent: 6639271 (2003-10-01), Zheng et al.
patent: 6735123 (2004-05-01), Tripsas et al.

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