Non-volatile and reconfigurable programmable logic devices

Details Non-volatile and reconfigurable programmable logic devices Non-volatile and reconfigurable programmable logic devices

2003-05-16

2004-12-07

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S046000

Reexamination Certificate

active

06828823

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to electrical circuits and, more particularly, to systems and methods for providing, programming, and configuring non-volatile and reconfigurable programmable logic devices.
BACKGROUND
There are many different types of programmable logic devices (PLDs), such as for example complex programmable logic devices (CPLDS) and field programmable gate arrays (FPGAs). CPLDs typically provide numerous benefits, such as fast, predictable timing and single-level wide-logic support. CPLDs generally utilize electrically erasable complementary metal oxide semiconductor (EECMOS) technology, which is non-volatile but can be programmed only a limited number of times and takes longer to program than some other types of memory (e.g., static random access memory (SRAM)).
FPGAs typically provide benefits, such as high logic density and low standby power and generally utilize SRAM technology. SRAM is infinitely reconfigurable, but loses its programming upon power loss and generally requires an external non-volatile source to supply it with configuration data upon power-up. Various types of non-volatile technology have been introduced for FPGAs to replace SRAM. For example, antifuse-based technology provides non-volatility, but can not be reprogrammed and so is not reconfigurable. As another example, flash-based technology also provides non-volatility, but is not infinitely reconfigurable. Other types of non-volatile technology have been introduced, but typically suffer from various drawbacks, such as limited programmability. As a result, there is a need for improved programmable logic devices and techniques for programming the programmable logic devices.
SUMMARY
Systems and methods are disclosed herein to provide non-volatile and reconfigurable programmable logic devices. For example, in accordance with one embodiment of the present invention, EECMOS memory and SRAM are incorporated into a PLD to provide in-system programmability, dynamic reconfigurability, and essentially instant-on capability. The EECMOS memory technology eliminates the need for external configuration devices that are typically required for SRAM-based PLDs. The SRAM technology provides infinite reconfigurability, which is generally not available with EECMOS-based PLDs. Furthermore, flexible programming or configuration techniques are provided to supply configuration data to the EECMOS memory, the SRAM, or from the EECMOS memory to the SRAM.
More specifically, in accordance with one embodiment of the present invention, an integrated circuit includes volatile memory adapted to configure the integrated circuit for its intended function based on configuration data stored by the volatile memory; non-volatile memory adapted to store data which is transferable to the volatile memory to configure the integrated circuit; and a first data port adapted to receive external data for transfer into either the volatile memory or the non-volatile memory.
In accordance with another embodiment of the present invention, a programmable logic device includes volatile memory adapted to store configuration data to configure the programmable logic device; non-volatile memory adapted to store data and transfer the data to the volatile memory to configure the programmable logic device; and means for receiving external data and transferring the external data to the volatile memory or the non-volatile memory.
In accordance with another embodiment of the present invention, a method of providing programming and configuration options for a programmable logic device includes providing at least one data port adapted to receive configuration data; providing non-volatile memory, within the programmable logic device, adapted to receive the configuration data via at least one of the data ports; and providing volatile memory adapted to receive the configuration data via at least one of the data ports or via the non-volatile memory, the volatile memory further adapted to configure the programmable logic device for its intended function.
In accordance with another embodiment of the present invention, a programmable logic device includes volatile memory adapted to configure the programmable logic device for its intended function based on configuration data stored by the volatile memory; non-volatile memory adapted to store data which is transferable to the volatile memory to configure the programmable logic device, the non-volatile memory disposed within one or more areas of the programmable logic device that are separate from the volatile memory; and control logic adapted to transfer the data from the non-volatile memory to the volatile memory to configure the programmable logic device.
The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.


REFERENCES:
patent: 5548228 (1996-08-01), Madurawe
patent: 5640107 (1997-06-01), Kruse
patent: 5696455 (1997-12-01), Madurawe
patent: 6049222 (2000-04-01), Lawman
patent: 6538468 (2003-03-01), Moore

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