Non-unique results in design verification by test programs

Details Non-unique results in design verification by test programs Non-unique results in design verification by test programs

2002-01-10

2011-11-08

Shah, Kamini S (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

C703S001000, C703S021000, C703S022000, C711S141000, C711S144000, C711S146000, C712S025000, C714S010000, C714S021000, C714S025000, C714S037000, C714S042000, C716S106000, C716S136000

Reexamination Certificate

active

08055492

ABSTRACT:
A design verification system that verifies the operation of multi-processor architecture by generating test programs in which the behavior of the processor, when executing the test program, is evaluated against the behavior required by the design specification. The test program generator produces scenarios for a multi-processor design in which non-unique results may occur. The system is provided with facilities to report expected outcomes, and to evaluate the validity of non-unique results in multiple resources under conditions of non-unique result propagation and dependencies among adjacent and non-adjacent resources.

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