Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2006-05-30
2006-05-30
Phan, Trong (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185240
Reexamination Certificate
active
07054193
ABSTRACT:
Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operation reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing. During or at the end of write operations, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly.
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Phan Trong
Samsung Electronics Co,. Ltd.
Volentine Francos & Whitt pllc
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