Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-17
2004-03-23
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S202000, C257S401000
Reexamination Certificate
active
06710405
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices, and more specifically to semiconductor devices having repeated cell structures. In particular the invention is directed to semiconductor power devices which comprise one or more arrays of active cells (transistors), but is applicable in devices such as semiconductor memories which comprise one or more arrays of repeated active cells, namely, memory cells.
Semiconductor power devices (e.g., metal oxide semiconductor field effect transistors, MOSFETs) are designed and manufactured with a repetitive structure. The repeated structure comprises patterns of one or more repetitive cell (transistor) structures and ancillary elements.
FIG. 6A
shows a semiconductor die
601
of a conventional semiconductor power device and its constituent structures. A main active area
602
of the device die comprises a repetition of one type of transistor, sometimes referred to as a cell or a main cell of the device. This is designated in the figure by the letter A (the “A cells”).
The active area is the main area of the power device, typically located within a region bounded by an edge termination area. The edge termination area usually does not contain active transistors, what are commonly referred to as active devices. In the industry, passive devices, the opposite of active devices, include resistors, capacitors and inductors. The edge of the power device is composed of guard rings, or field shielding plates, that serve to provide the device with a high breakdown capability. Since this section is on the periphery and includes mainly floating junctions or field plates, which are different from the main transistor of the power device, this section is not called the active area. The area that is contained by the edge section, and has the main active cells of the device, that define and control its operational function is the active area. In a power device, such as one described and claimed in this specification, there is a parallel combination of a multitude of active device cells, with the same overall physics of device operation. The multitude of active device cells are operatively and turned on in parallel with the same control signal, constitute the operation of the main device. This region is the active region for the purpose of this application.
As noted above, a guard ring region
604
constitutes a non-active area which includes the very edges of the device die, and is sometimes referred to as the die termination area. The guard ring region does not contain active transistor cells, such as those contained within the area bounded by the guard ring region.
A peripheral section of the active area
602
of the semiconductor power device adjacent the guard ring region comprises another type of repetitive cell structure identified in the figure by the letter B (the “B cells”). These cells are commonly referred to as termination structures or end structures. They serve to seal off the edges of the active area
602
to provide for reliable device operation by preventing spurious edge effects due to high voltage differentials between the boundary of the active area and the edge of the device. In most cases, the peripheral section does not contain A cells.
The interior of the active area
602
further includes a region
608
which surrounds a gate bond pad
611
and regions
606
which surround gate finger segments
612
L,
612
R,
612
C, and
612
T. The cells which populate regions
606
and
608
are identified by the letter C (the “C cells”). The C cells are edge cells like the B cells in their role in a semiconductor power device. Since the left and/or right sides of the semiconductor chip might be different than the bottom or the top sides of the chip, in a general case, cells B and cells C might be different in structure. Further, it is standard die layout practice that the B and C cells might be varied in dimension and structure in order for them to fit geometrically and physically in their designated areas. For purposes of discussion, to distinguish the A cells which are the workhorses of the power device and the B and C cells, the A cells are referred to as the active cells, while the B and C cells are collectively referred to as the peripheral cells.
The B and C cells are the cells that interface or buffer the active area from the effects of the edge termination area. The edge termination area, usually has a higher electric field in the OFF state. Consequently, upon switching the device from the OFF state to the ON state and vice versa, transient voltage effects like dV/dt can generate extra holes and electrons in the semiconductor material near the edge of the chip, which will be flowing to the active area via the periphery cells B and C. Therefore, these cells should have a good short path to ‘ground’ potential in a typical n-channel power MOSFET, IGBT, or a thyristor of which the top surface, source, emitter or cathode is connected to ground. In other words the B and C cells are not active device cells like the more internal active cells, like A's in FIG.
6
A. In a typical device, such as MOSFET or IGBT, these peripheral cells will not have any n
+
source or emitter areas, comprising just the corresponding p
+
/p
−
well or base region with a relatively large contact area to the top source or emitter metal that is usually connected to the lowest potential, ground in most cases. These cells might contain edge sections of the poly-silicon gate, for MOS type power transistors, for the purpose of connectivity only. Thus, a gate metal line is disposed about the periphery and is contacted to the poly-silicon gate area in these periphery cells too. This gate metal line makes contact to the poly-silicon in these periphery cells, in its part that is removed from the metal and contact area that is connected to the source, emitter or ground potentia area.
Referring to
FIG. 6B
, another layout example of a conventional power device die
631
is shown. The active area
602
which provides the function of the power device comprises active cells A. The active area is surrounded by B cells, which are known as periphery termination cells. In addition, these types of cells typically are found disposed about the gate bus area, because of similar transient voltage effects in its vicinity, much like the edge termination area.
In some devices, a portion of the active area
602
extends beneath the source (or emitter) bond pads
614
so that the area beneath the bond pads is populated with A cells. Other applications call for the portion of the active area beneath the source (or emitter) bond pads to be populated with modified cells. See for example, U.S. Pat. No. 4,881,106. In some special cases, the application may call for a power device die in which the portion of the active area beneath the bond pad is absent cells of any kind.
Some power device applications incorporate specialized cells in the active area
602
that do not serve as an active cell. For example, temperature sensing cells can be incorporated in the active area to provide an indicator of the device temperature. Other sensors include current sensors. See also, U.S. Pat. Nos. 5,237,481 and 5,063,307. However, special application power devices aside, the active area
602
typically comprises a regular uniform pattern of A cells. A common shape is the hexagon, though square-shaped and triangular-shaped cells are known. Also, cells having a linear (striped) geometry are in use.
Limitations in the performance of conventional power devices arise from the fact that various physical characteristics of such a device during its operation do not manifest themselves uniformly throughout the device. For example, the temperature rise varies depending on the location on the die; e.g., the center of the die typically is the hottest region of the device. The distribution of electric current in the active area
602
varies due in part to the non-uniform temperature distribution, which tends to create a situation known as “current hogging.” This in turn
Tsukanov Vladimir
Zommer Nathan
Ixys Corporation
Loke Steven
LandOfFree
Non-uniform power semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-uniform power semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-uniform power semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3280509