Non-uniform gate doping for reduced overlap capacitance

Details Non-uniform gate doping for reduced overlap capacitance Non-uniform gate doping for reduced overlap capacitance

1999-07-20

2001-05-08

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

With specified impurity concentration gradient

C257S607000, C257S412000

Reexamination Certificate

active

06229198

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device comprising transistors and a method for manufacturing the device. The present invention has particular applicability in manufacturing metal oxide semiconductor field effect transistors (MOSFETs) with submicron dimensions.
BACKGROUND ART
Over the last few decades, the electronics industry has undergone a revolution in fabricating miniaturized and highly integrated semiconductor devices. The most common semiconductor device is a metal oxide semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor generally comprise a semiconductor substrate on which a gate electrode is disposed. The gate electrode is typically a heavily doped conductor having uniform conductivity. An input signal is typically applied to the gate electrode via a gate terminal. Heavily doped source/drain regions are formed in the semiconductor substrate and are connected to source/drain terminals. The typical MOS transistor is symmetrical, in that the source and drain regions are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device, e.g., PMOS or NMOS. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The gate electrode is generally separated from the semiconductor substrate by an insulating layer, e.g., an oxide layer, to prevent current from flowing between the gate electrode and the source/drain regions or channel regions.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electrical field is set up in the channel region. By varying the transverse electric field between the source and drain regions, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner, an electric field controls the current flow through the channel region. This type of devices is commonly referred to as a MOSFET.
In MOSFET devices, the voltage potentials of an operative transistor create a number of capacitance loads which adversely affect transistor performance. Among the capacitance loads developed in a MOSFET, an overlap capacitance is normally observed between the gate electrode and an adjacent drain region. The overlap capacitance is a function of the extent of overlap between the gate electrode and the underlying drain region as well as the thickness of the gate oxide layer. The overlap capacitance contributes to noise and tends to reduce the switching speed of the transistor, both of which are undesirable from a performance standpoint.
Various approaches have been proposed to reduce the vertical electric field effect and overlap capacitance. According to the method disclosed in U.S. Pat. No. 5,804,496 issued to Michael Duane, a gate electrode is formed by multiple ion implantation steps to reduce the conductivity of both edge portions or to dope the edge portions with a different conductivity than the central portion of the gate electrode. As shown in
FIG. 1
, an oxide layer
12
is formed on a substrate
10
, and a gate electrode
14
is formed on a oxide layer
12
. As shown in
FIG. 2
, ion implantation is then conducted, as indicated by arrow A, to form shallow source/drain extension
20
extending under the gate electrode
14
at a predetermined distance, which is a primary factor in the overlap capacitance of conventional semiconductors. As shown in
FIG. 3
, an edge dopant is implanted into the first edge portion
30
of the gate electrode
14
at a predetermined angle, as shown by arrow B. Subsequently, the second edge portion
40
is also ion implanted with the edge dopant at the predetermined angle, as shown by arrow C in
FIG. 4. A
spacer layer
50
is then formed on the surface of the substrate
10
including gate electrode
14
, as shown in FIG.
5
. Sidewall spacers
60
are then formed on the side surfaces of gate electrode
14
, as shown in FIG.
6
. Then, a gate dopant is ion implanted as shown by arrows D in
FIG. 7
, into gate electrode
14
including edge portions
30
and
40
, and to form source/drain regions
70
. The edge portions
30
and
40
of the gate electrode
14
contain the edge dopant which either inhibits diffusion of the gate dopant or has a different conductive type than the gate dopant. Therefore, gate dopant implantation, the edge portions
30
and
40
have reduced conductivity. Advancing to
FIG. 14
, the edge dopant profile of Duane's gate electrode is shown by curve N, and an actual gate impurity profile after the gate dopant implantation is shown by curve B. The gate dopant concentration level at the edge portions G
D
-D
G
and S
G
-G
S
is lower than the central portion D
G
-S
G
of Duane's gate electrode, thereby reducing the overlap capacitance formed between the edge portions
30
,
40
and the source and drain regions
70
. It is known that such overlap capacitance degrades the device speed, but the overlap capacitance formed between the gate electrode and source region dose not adversely impact device speed. In addition, as shown in
FIG. 14
, the significantly reduced amount of the gate dopant at both side portions of the gate electrode weakens the transverse electrical field in the channel region.
Accordingly, there exists a need for a semiconductor device exhibiting reduced overlap capacitance, and an efficient and production worthy method for manufacturing such a semiconductor device.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is simplified and production worthy methodology for manufacturing a MOSFET exhibiting reduced overlap capacitance.
Another advantage of the present invention is a semiconductor device exhibiting reduced overlap capacitance.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The objects and advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing semiconductor device, the method comprising: forming a dielectric layer on a main surface of a semiconductor substrate; forming a conductive layer on the dielectric layer, having first and second side portions; and ion implanting impurity atoms into the conductive layer to form an impurity concentration profile increasing from the first side portion to the second side portion.
Another aspect of the present invention is a semiconductor comprising: a substrate; source/drain regions in the substrate with a channel region therebetween; a gate dielectric layer on the substrate overlying the channel region; and a gate electrode on the gate dielectric layer, the gate electrode having a graded impurity concentration profile laterally increasing from a first side portion to a second side portion of the gate electrode.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.


REFERENCES:
patent: 5635749 (1997-06-01), Hong
patent: 5804496 (1998-09-01), Duane

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