Non-uniform cache apparatus, systems, and methods

Details Non-uniform cache apparatus, systems, and methods Non-uniform cache apparatus, systems, and methods

2005-11-15

2005-11-15

Bragdon, Reginald G. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S167000, C711S136000, C711S005000

Reexamination Certificate

active

06965969

ABSTRACT:
An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).

REFERENCES:
patent: 5619676 (1997-04-01), Fukuda et al.
patent: 6412038 (2002-06-01), Mehalel
patent: 6549987 (2003-04-01), Rappoport et al.
Kim, Changkyu et al. “An Adaptive Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches”, Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems; Oct. 2002.

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