Non-trenched buried contact for VLSI devices

Details Non-trenched buried contact for VLSI devices Non-trenched buried contact for VLSI devices

1994-12-12

1995-12-26

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257330, 257327, 257397, 257384, H01L 2701

Patent

active

054790417

ABSTRACT:
The invention describes a non-trenched buried contact for local interconnections in VLSI devices and provides a method for forming the non-trenched buried contact. By using trenched isolation and a trench polysilicon gate structure the buried contact process can be implemented so that there are no unwanted trenches formed in the area of the buried contact. The invention permits excellent planarization of the device prior to pre-metal dielectric and metal deposition.

REFERENCES:
patent: 4424621 (1984-01-01), Abbas et al.
patent: 4803176 (1989-02-01), Bower
patent: 4908688 (1990-03-01), Lund et al.
patent: 4945070 (1990-07-01), Hsu
patent: 5028555 (1991-07-01), Haskell
patent: 5089872 (1992-02-01), Ozturk et al.
patent: 5196368 (1993-03-01), Thompson et al.
patent: 5216282 (1993-06-01), Cote et al.
patent: 5334861 (1994-08-01), Pfiester et al.
"Simulation of Sub-0.1.-un MOSFET's with Completely Suppressed Short-Channel Effect" by Tanaka et al., in IEEE Electron Device Letters, Aug. 1993.

Affiliated with

Also associated with

Rating

Non-trenched buried contact for VLSI devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-trenched buried contact for VLSI devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-trenched buried contact for VLSI devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1370817