Non-synchronous semiconductor memory device having page mode...

Details Non-synchronous semiconductor memory device having page mode... Non-synchronous semiconductor memory device having page mode...

2006-05-30

2006-05-30

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189020, C365S238500

Reexamination Certificate

active

07054224

ABSTRACT:
The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit110holds data having been read out of memory cells in a memory cell array106designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1included in the address, a multiplexer111sequentially and non-synchronously feeds out the data held in the data latch circuit110based on the column addresses A0, A1.

REFERENCES:
patent: 4575825 (1986-03-01), Ozaki et al.
patent: 5404327 (1995-04-01), Houston
patent: 5619473 (1997-04-01), Hotta
patent: 5825709 (1998-10-01), Kobayashi
patent: 6337810 (2002-01-01), Yamasaki et al.
patent: 6629224 (2003-09-01), Suzuki et al.
patent: 59-3790 (1984-01-01), None
patent: 63-46697 (1988-02-01), None
patent: 1-94593 (1989-04-01), None
patent: 8-203274 (1996-08-01), None
patent: 2001-28190 (2001-01-01), None
patent: 2001-118395 (2001-04-01), None

Affiliated with

Also associated with

Rating

Non-synchronous semiconductor memory device having page mode... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-synchronous semiconductor memory device having page mode..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-synchronous semiconductor memory device having page mode... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3577498