Bus interface for processor

Details Bus interface for processor Bus interface for processor

2006-05-30

2006-05-30

Perveen, Rehana (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S313000

Reexamination Certificate

active

07054988

ABSTRACT:
The present invention may generally provide a processor circuit comprising a processor, a first bus, a bus pipeline stage, and a second bus. The first bus may be coupled to the processor. The bus pipeline stage may be coupled between the first bus and the second bus and configured to delay an access between the first bus and the second bus at least one pipeline cycle.

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