Non-sequential access pattern based address generator

Details Non-sequential access pattern based address generator Non-sequential access pattern based address generator

2006-09-26

2006-09-26

Dildine, R. Stephen (Department: 2133)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

C345S572000

Reexamination Certificate

active

07114023

ABSTRACT:
An address generator is provided with an input to receive a base address for an array of storage locations, an offset generator to generate a number of offsets, and a combiner coupled to the input and the offset generator to combine the base address with the offsets to generate a number of access addresses for accessing the array of storage locations in accordance with a deterministic access pattern having at least one non-sequential access. In various embodiments, the address generator is included in each of a number of signal processing units, which in turn are included in a digital media processor.

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