Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-10-09
2003-12-16
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S725000, C438S975000
Reexamination Certificate
active
06664191
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a method for producing small space patterns during fabrication of memory devices.
BACKGROUND
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photo mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through the photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The spacing between adjacent lines of an integrated circuit is an important dimension, and ever continuing efforts are made toward reducing such spacing dimension. The wavelength of light used in the photolithographic process along with the lithographic tool set employed in the process generally dictate the spacing dimension. For example, a tool set designed to provide lines and/or spaces at 0.12 &mgr;m does not achieve consistent lines and/or spacing at its minimum range of 0.12 &mgr;m but rather is employed to generate lines and/or spacing above the minimum range (e.g., 0.14 &mgr;m) with fairly consistent results.
Conventional flash memory cells allow for a high packing density. Each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bit line. The width of the word lines and conductive bit lines are limited by the wavelength of light used in the photolithographic process along with the lithographic tool set employed in the process of fabricating the trenches for forming the bit lines. Furthermore, shallow trench isolation (STI) has been gradually replacing LOCOS in fabrication of memory devices due to its improved utilization of real state. However, the use of STI also contributes to problems associated with consistent lines and/or spacing at a minimum range of the lithographic tool due to overlay issues that exist around the STI edges.
In view of the above, it would be desirable for a technique which allows for a particular lithographic tool set to be employed and achieve consistent lines and/or spacing between lines at the minimum range of the tool set and even below the minimum range during fabrication of memory cells employing a STI process.
SUMMARY
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a method of fabricating memory cells employing a non self-aligned STI process. The present invention employs a photolithographic tool set and achieves substantially consistent spacing dimensions below the minimum range of the tool set during fabrication of stacked floating gate memory cells using shallow trench isolation (STI) regions between memory cells. STI regions are formed in both a core region and a periphery region of a substrate. A first polysilicon layer is formed over the substrate and the STI regions. The first polysilicon layer is planarized by a chemical mechanical polish (CMP) to eliminate STI overlay issues. A stop layer and a mask layer (e.g., SiN layer) are then deposited over the planarized polysilicon layer. A photoresist layer is deposited over the mask layer. A given photolithographic tool set is employed to pattern a photoresist layer in a desired fashion. The tool set is capable of achieving a smallest spacing dimension between adjacent lines of d
1
.
After the photoresist layer is patterned, an etch step is performed to etch the pattern in the underlying mask layer. The photoresist layer is then stripped from the mask layer. Next, a nitride layer is conformably deposited over the patterned mask layer. Thereafter, a directional etch is performed to remove a particular amount of the nitride layer (preferably a thickness equivalent to the thickness of the nitride layer residing over the mask layer). The directional etch leaves nitride sidewalls along the patterned mask layer which result in a reduction in dimension size of exposed areas interposed between adjacent mask portions. Thus, a spacing dimension size (d
2
) of exposed areas is substantially less than the spacing dimension size (d
1
) of exposed areas prior to the depositing the nitride layer. An etch step is performed to etch layers underlying the mask layer. Adjacent lines etched from one of the underlayers will have a smallest spacing design dimension of d
2
as compared to d
1
. Thus, the present invention provides for achieving spacing dimensions between lines at and below a minimum patterning range for a particular lithographic tool set.
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Chang Chi
Hui Angela T.
Kim Unsoon
Sun Yu
Templeton Michael K.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Chen Kin-Chan
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