Non-random sub-lithography vertical stack capacitor

Details Non-random sub-lithography vertical stack capacitor Non-random sub-lithography vertical stack capacitor

1994-07-22

1996-07-23

Dang, Thi

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

1566571, 1566551, 15666111, 437228, 437919, H01L 2100

Patent

active

055385923

ABSTRACT:
Integrated circuit structures of sub-lithography dimensions are formed by conformal deposition of alternating layers of materials having differing etch rates within an aperture over a body of material to be etched. One of the materials in the alternating layers is then selectively and preferentially etched to form a mask through which etching can be performed on the body of material to be etched. This technique is particularly suited to the formation of structurally robust capacitors for memory cells which have greatly increased plate area, resulting in increased capacitance, while maintaining a small footprint for the capacitor structure.

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patent: 5231044 (1993-07-01), Jun
patent: 5340763 (1994-08-01), Dennison
patent: 5416037 (1995-05-01), Sato et al.

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