Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-05-13
2001-11-06
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S152000, C711S151000, C711S150000, C711S149000
Reexamination Certificate
active
06314499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the shared usage of synchronous memory by a plurality of processing agents, e.g., processors.
2. Background of Related Art
With the ever-increasing speeds of today's processors, memory designs have attempted to meet the required speed requirements. For instance, synchronous memory such as synchronous static random access memory (SSRAM) and synchronous dynamic random access memory (SDRAM) are commonly available synchronous types of memory.
Synchronous memory technology is currently used in a wide variety of applications to close the gap between the needs of high-speed processors and the access time of asynchronous memory such as dynamic random access memory (DRAM). Synchronous memory, e.g., SDRAM technology, combines industry advances in fast dynamic random access memory (DRAM) with a high-speed interface.
Functionally, an SDRAM resembles a conventional DRAM, i.e., it is dynamic and must be refreshed. However, the SDRAM architecture has improvements over standard DRAMs. For instance, an SDRAM may use internal pipelining to improve throughput and on-chip interleaving between separate memory banks to eliminate gaps in output data.
The idea of using a SDRAM synchronously (as opposed to using a DRAM asynchronously) emerged in light of increasing data transfer demands of high-end processors. SDRAM circuit designs are based on state machine operation instead of being level/pulse width driven as in conventional asynchronous memory devices. Instead, the inputs are latched by the system clock. Since all timing is based on the same synchronous clock, designers can achieve better specification margins. Moreover, since the SDRAM access is programmable, designers can improve bus utilization because the processor can be synchronized to the SDRAM output.
The core of an SDRAM device is a standard DRAM with the important addition of synchronous control logic. By synchronizing all address, data and control signals with a single clock signal, SDRAM technology enhances performance, simplifies design and provides faster data transfer.
Similar advantages hold for other types of synchronous memory, e.g., SSRAM or even synchronous read only memory.
Synchronous memory requires a clock signal from the accessing agent to allow fully synchronous operation with respect to the accessing agent. If more than one agent is given access to a shared synchronous memory, each agent must conventionally supply its own clock signal to the synchronous memory. Unfortunately, the clock signals from separate agents are not conventionally synchronous or in phase with one another. Therefore, if a synchronous memory were to be shared among a plurality of agents, delays or wait states would be required to allow an error-free transition between access by a first agent having a first synchronous memory access clock signal and a subsequent access by another agent having a different synchronous memory access clock signal.
Some synchronous memory devices have the capability to provide burst input/output (I/O), particularly for the optimization of cache memory fills at the system frequency. Advanced features such as programmable burst mode and burst length improve memory system performance and flexibility in conventional synchronous memories, and eliminate the need to insert otherwise unnecessary wait states, e.g., dormant clock cycles, between individual accesses in the burst.
Conventional SDRAM devices include independent, fixed memory sections that can be accessed individually or in an interleaved fashion. For instance, two independent banks in an SDRAM device allow that device to have two different rows active at the same time. This means that data can be read from or written to one bank while the other bank is being precharged. The setup normally associated with precharging and activating a row can be hidden by interleaving the bank accesses.
FIG. 11
shows a conventional synchronous memory system having only one agent
100
and a synchronous memory, e.g., SDRAM
502
. The single agent
100
communicates with the synchronous memory using appropriate address, data and control buses (ADC)
506
, and one or more clock signals
504
. Because the synchronous memory
502
has only the single accessing agent
100
, the synchronous memory
302
need only contend with access from a single source.
Conventional processing systems utilizing a plurality of agents have separate memory for each agent. However, depending upon the particular application, it is likely that all memory will not be used by all agents at all times, and thus wasted memory resources may result in each of the separate memories.
There is thus a need for synchronous memory systems which allow efficient use of synchronous memory resources by a plurality of agents.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a non-preemptive arbitration system comprises a pre-arbiter to condition memory access request signals from a plurality of agents sharing a common resource. An arbiter arbitrates and selects one of the plurality of agents for subsequent access to the common resource. The pre-arbiter is capable of conditioning the memory access request signals by suppressing subsequent memory access signals from one of the plurality of agents which currently accesses the common resource when a locking memory access request signal is received from another one of the plurality of agents.
A method of arbitrating from among a plurality of resource request signals for access to a common resource in accordance with the principles of the present invention comprises providing access to the common resource by a first agent. Memory access request signals from the first agent to an arbitrator are monitored, and an inactive memory access cycle in the first agent's access to the common resource is determined. A second agent is allowed to access the common resource during the inactive memory access cycle in the first agent's access to the common resource.
REFERENCES:
patent: 5175837 (1992-12-01), Arnold et al.
patent: 5557783 (1996-09-01), Oktay et al.
patent: 5566123 (1996-10-01), Freidin
patent: 5659711 (1997-08-01), Sugita
patent: 5802581 (1998-09-01), Nelsen
patent: 5802597 (1998-09-01), Nelsen
patent: 5826056 (1998-10-01), Noda
patent: 5844856 (1998-12-01), Taylor
patent: 5933855 (1999-08-01), Rubinstein
patent: 5991230 (1998-12-01), Urakawa
patent: 6006319 (1999-12-01), Takahashi et al.
patent: 6014729 (2000-01-01), Lannan et al.
patent: 6032232 (2000-02-01), Lindeborg et al.
patent: 6035360 (2000-03-01), Doidge et al.
Bollman William H.
Lucent Technologies - Inc.
McLean Kimberly
Yoo Do Hyun
LandOfFree
Non-preemptive memory locking mechanism in a shared resource... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-preemptive memory locking mechanism in a shared resource..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-preemptive memory locking mechanism in a shared resource... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2615062