Non-plasma capping layer for interconnect applications

Details Non-plasma capping layer for interconnect applications Non-plasma capping layer for interconnect applications

2011-01-18

2011-01-18

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C257SE21224, C257SE21575, C438S675000, C438S687000

Reexamination Certificate

active

07871935

ABSTRACT:
The present invention provides an interconnect structure which has a high leakage resistance and substantially no metallic residues and no physical damage present at an interface between the interconnect dielectric and an overlying dielectric capping layer. The interconnect structure of the invention also has an interface between each conductive feature and the overlying dielectric capping layer that is substantially defect-free. The interconnect structure of the invention includes a non-plasma deposited dielectric capping layer which is formed utilizing a process including a thermal and chemical-only pretreatment step that removes surface oxide from atop each of the conductive features as well as metallic residues from atop the interconnect dielectric material. Following this pretreatment step, the dielectric capping layer is deposited.

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