Non-planar transistor and techniques for fabricating the same

Details Non-planar transistor and techniques for fabricating the same Non-planar transistor and techniques for fabricating the same

2006-05-12

2009-08-11

Lee, Hsien-ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S287000, C257SE21444, C438S283000, C438S164000, C438S149000

Reexamination Certificate

active

07573108

ABSTRACT:
A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first voltage that is configured to turn on the transistor, and the passive gate may be fixedly coupled to a second voltage different than the first voltage. In some embodiments, the difference in voltage between the first voltage and the second voltage is greater than or substantially equal to a difference in voltage between the first voltage and a substrate voltage.

REFERENCES:
patent: 2005/0093067 (2005-05-01), Yeo et al.
patent: 2007/0076477 (2007-04-01), Hwang et al.
patent: WO 2004/038770 (2004-05-01), None
T. Park, et al.; “Fabrication of Body-Tied FinFETs (Oega MOSFETs) Using Bulk Si Wafers”;2003 Symposium on VLSI Technology Digest of Technical Papers; Jun. 2003, 2 pages.
R. Katsumata, et al.; “Fin-Array-FET on bulk silicon for sub-100 nm Trench Capacitor DRAM”;2003 Symposium on VLSI Technology Digest of Technical Papers; Jun. 2003, 2 pages.

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