Non-planar pMOS structure with a strained channel region and...

Details Non-planar pMOS structure with a strained channel region and... Non-planar pMOS structure with a strained channel region and...

2008-03-25

2008-03-25

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Germanium or silicon or ge-si on iii-v

C257SE29193

Reexamination Certificate

active

07348284

ABSTRACT:
A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-xGexlayer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-xGexlayer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-yGeylayer, having the Ge content y higher than the Ge content x in the relaxed Si1-xGexlayer, is epitaxially grown on the fin. The Si1-yGeylayer covers the top and two sidewalls of the fin. The compressive stress in the Si1-yGeylayer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.

REFERENCES:
patent: 4906589 (1990-03-01), Chao
patent: 4996574 (1991-02-01), Shirasaki et al.
patent: 5124777 (1992-06-01), Lee
patent: 5338959 (1994-08-01), Kim et al.
patent: 5346839 (1994-09-01), Sundaresan
patent: 5391506 (1995-02-01), Tada et al.
patent: 5466621 (1995-11-01), Hisamoto et al.
patent: 5545586 (1996-08-01), Koh
patent: 5563077 (1996-10-01), Ha
patent: 5578513 (1996-11-01), Maegawa
patent: 5595919 (1997-01-01), Pan
patent: 5658806 (1997-08-01), Lin et al.
patent: 5701016 (1997-12-01), Burroughes et al.
patent: 5716879 (1998-02-01), Choi et al.
patent: 5793088 (1998-08-01), Choi et al.
patent: 5804848 (1998-09-01), Mukai
patent: 5814895 (1998-09-01), Hirayama et al.
patent: 5821629 (1998-10-01), Wen et al.
patent: 5827769 (1998-10-01), Aminzadeh et al.
patent: 5844278 (1998-12-01), Mizuno et al.
patent: 5888309 (1999-03-01), Yu
patent: 5899710 (1999-05-01), Mukai
patent: 5905285 (1999-05-01), Gardner et al.
patent: 6018176 (2000-01-01), Lim
patent: 6066869 (2000-05-01), Noble et al.
patent: 6163053 (2000-12-01), Kawashima
patent: 6252284 (2001-06-01), Muller et al.
patent: 6307235 (2001-10-01), Forbes et al.
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6383882 (2002-05-01), Lee et al.
patent: 6396108 (2002-05-01), Krivokapic et al.
patent: 6407442 (2002-06-01), Inoue et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6413877 (2002-07-01), Annapragada
patent: 6459123 (2002-10-01), Enders et al.
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6475869 (2002-11-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6583469 (2003-06-01), Fried et al.
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6630388 (2003-10-01), Ishii et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6645797 (2003-11-01), Buynoski et al.
patent: 6657259 (2003-12-01), Fried et al.
patent: 6680240 (2004-01-01), Maszara
patent: 6689650 (2004-02-01), Gambino et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 6713396 (2004-03-01), Anthony
patent: 6716684 (2004-04-01), Krivokapic et al.
patent: 6716690 (2004-04-01), Wang et al.
patent: 6730964 (2004-05-01), Horiuchi
patent: 6756657 (2004-06-01), Zhang et al.
patent: 6764884 (2004-07-01), Yu et al.
patent: 6770516 (2004-08-01), Wu et al.
patent: 6787402 (2004-09-01), Yu
patent: 6790733 (2004-09-01), Natzle et al.
patent: 6794313 (2004-09-01), Chang
patent: 6794718 (2004-09-01), Nowak et al.
patent: 6798000 (2004-09-01), Luyken et al.
patent: 6800910 (2004-10-01), Lin et al.
patent: 6803631 (2004-10-01), Dakshina-Murthy et al.
patent: 6812075 (2004-11-01), Fried et al.
patent: 6815277 (2004-11-01), Fried et al.
patent: 6821834 (2004-11-01), Ando
patent: 6833588 (2004-12-01), Yu et al.
patent: 6835614 (2004-12-01), Hanafi et al.
patent: 6835618 (2004-12-01), Dakshina-Murthy et al.
patent: 6849884 (2005-02-01), Clark et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 6869868 (2005-03-01), Chiu et al.
patent: 6884154 (2005-04-01), Mizushima et al.
patent: 6885055 (2005-04-01), Lee
patent: 6897527 (2005-05-01), Dakshina-Murthy et al.
patent: 6921982 (2005-07-01), Joshi et al.
patent: 2002/0011612 (2002-01-01), Hieda
patent: 2002/0036290 (2002-03-01), Inaba et al.
patent: 2002/0081794 (2002-06-01), Ito
patent: 2002/0166838 (2002-11-01), Nagarajan
patent: 2002/0167007 (2002-11-01), Yamazaki et al.
patent: 2003/0042542 (2003-03-01), Maegawa et al.
patent: 2003/0057486 (2003-03-01), Gambino et al.
patent: 2003/0067017 (2003-04-01), Ieong et al.
patent: 2003/0085194 (2003-05-01), Hopkins, Jr.
patent: 2003/0098488 (2003-05-01), O'Keeffe et al.
patent: 2003/0102497 (2003-06-01), Fried et al.
patent: 2003/0102518 (2003-06-01), Fried et al.
patent: 2003/0111686 (2003-06-01), Nowak
patent: 2003/0122186 (2003-07-01), Sekigawa et al.
patent: 2003/0143791 (2003-07-01), Cheong et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2003/0201458 (2003-10-01), Clark et al.
patent: 2003/0227036 (2003-12-01), Sugiyama et al.
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 2004/0036118 (2004-02-01), Abadeer et al.
patent: 2004/0036126 (2004-02-01), Chau et al.
patent: 2004/0036127 (2004-02-01), Chau et al.
patent: 2004/0061178 (2004-04-01), Lin et al.
patent: 2004/0070020 (2004-04-01), Fujiwara et al.
patent: 2004/0092062 (2004-05-01), Ahmed et al.
patent: 2004/0092067 (2004-05-01), Hanafi et al.
patent: 2004/0094807 (2004-05-01), Chau et al.
patent: 2004/0110097 (2004-06-01), Ahmed et al.
patent: 2004/0119100 (2004-06-01), Nowak et al.
patent: 2004/0126975 (2004-07-01), Ahmed et al.
patent: 2004/0145019 (2004-07-01), Dakshina-Murthy et al.
patent: 2004/0180491 (2004-09-01), Arai et al.
patent: 2004/0191980 (2004-09-01), Rios et al.
patent: 2004/0195624 (2004-10-01), Liu et al.
patent: 2004/0198003 (2004-10-01), Yeo et al.
patent: 2004/0219780 (2004-11-01), Ohuchi
patent: 2004/0227187 (2004-11-01), Cheng et al.
patent: 2004/0238887 (2004-12-01), Nihey
patent: 2004/0256647 (2004-12-01), Lee et al.
patent: 2004/0262683 (2004-12-01), Bohr et al.
patent: 2004/0262699 (2004-12-01), Rios et al.
patent: 2005/0035415 (2005-02-01), Yeo et al.
patent: 2005/0093154 (2005-05-01), Kottantharayil et al.
patent: 2005/0118790 (2005-06-01), Lee et al.
patent: 2005/0127362 (2005-06-01), Zhang et al.
patent: 2005/0145941 (2005-07-01), Bedell et al.
patent: 2005/0156171 (2005-07-01), Brask et al.
patent: 2005/0184316 (2005-08-01), Kim
patent: 2005/0224797 (2005-10-01), Ko et al.
patent: 2005/0224800 (2005-10-01), Lindert et al.
patent: 2005/0227498 (2005-10-01), Furkawa
patent: 2005/0230763 (2005-10-01), Huang et al.
patent: 2006/0014338 (2006-01-01), Doris et al.
patent: 0 623 963 (1994-11-01), None
patent: 1 202 335 (2002-05-01), None
patent: 1 202 335 (2002-05-01), None
patent: 1 566 844 (2005-08-01), None
patent: 406177089 (1994-06-01), None
patent: 2003-298051 (2003-10-01), None
patent: 2003298051 (2003-10-01), None
patent: WO 02/43151 (2002-05-01), None
patent: WO 02/43151 (2002-05-01), None
patent: WO 2004/059726 (2004-07-01), None
patent: PCT/US2005/010505 (2005-03-01), None
Burenkov, A. et al., “Corner Effect in Double and Triple Gate FINFETs”, European Solid-State Device Research, 2003 33rdConference on Essderc Sep. '03, 2003, Piscataway, NJ, USA, IEEE, pp. 135-138, XP010676716.
Chang, S.T. et al, “3-D Simulation of Strained Si/SiGe Heterojunction FinFETS”, Semiconductor Device Research Symposium, 2003 International, Dec. 2003, Piscataway, NJ, USA, IEEE, pp. 176-177, XP010687197.
V. Subramanian et al., “A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100m MOSFETS” Proceeding of the 57th Annual Device Research Conference, pp. 28-29 (1999).
Hisamoto et al., “A Folded-channel MOSFET for Deep sub-tenth Micron Era”, 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034 (1998).
Huang et al., “Sub 50-nm FinFET: PMOS”, 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70 (1999).
Auth et al., “Vertical, Fully-Depleted, Surroundings Gate MOSFETS On sub-0.1um Thick Silicon Pillars”, 1996 54th Annual Device Research Conference Digest, pp. 108-109 (1996).
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