Non-planar non-volatile memory cell with an erase gate, an...

Details Non-planar non-volatile memory cell with an erase gate, an... Non-planar non-volatile memory cell with an erase gate, an...

2006-10-31

2006-10-31

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S319000, C257S320000, C257S322000, C257S622000, C438S689000

Reexamination Certificate

active

07129536

ABSTRACT:
A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

REFERENCES:
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patent: 6958273 (2005-10-01), Chen et al.

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