Non-overlapping clock generation

Details Non-overlapping clock generation Non-overlapping clock generation

2002-12-20

2004-09-28

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S096000, C327S239000, C327S259000, C327S295000

Reexamination Certificate

active

06798248

ABSTRACT:

BACKGROUND
Multiple clock signals can coordinate the operation of circuit elements in a microprocessor. For example, two out of phase clock signals can coordinate the operation of a shift register or scan chain circuit. Moreover, the clock signals may be generated in a “non-overlapping” fashion to prevent data race-through in the circuit (e.g., two successive latches will not pass data at the same time). That is, the clock signals may be generated such that both clocks signals are not active at the same time.
As another example, two out of phase clock signals can be provided to a simple switched-mode Direct Current (DC) to DC converter (e.g., a buck converter or a switched capacitor converter). In this case, an inductor or a capacitor accumulates energy from an input power supply during one phase, and the accumulated energy is transferred to the output of the converter during another phase. Once again the clock signals may be generated in a non-overlapping fashion, because an accidental overlap of the two phases might short circuit the input power supply (e.g., wasting power and perhaps damaging devices in the circuit).
FIG. 1
illustrates a known circuit
100
that can generate two-phase, non-overlapping clock signals (i.e., CLKA and CLKB). An input clock signal (i.e., CLKIN) is provided to a first NAND gate
110
and an inverted CLKIN is provided to a second NAND gate
120
(e.g., after CLKIN passes through an inverter
150
). The output of the first NAND gate
110
is coupled to a non-inverting delay element
130
that introduces a delay of T. The output of the delay element
130
is coupled to both an input of the second NAND gate
120
and an inverter
140
that provides CLKA. Similarly, the output of the second NAND gate
120
is coupled to another delay element
130
, which in turn is coupled to both an input of the first NAND gate
110
and an inverter
140
that provides CLKB.
As can be seen by the clock waveforms illustrated in
FIG. 1
, the two clock signals generated by the circuit
100
are out of phase. Moreover, to ensure that CLKA and CLKB are non-overlapping (e.g., that no accidental overlap occurs because of skew, jitter, or degraded rise and fall times in a clock signal), a dead time is provided. Thus, there are periods of time when both CLKA and CLKB are not active (the cross-hatched areas).
One disadvantage to this approach is that the operation of the circuit
100
is dependent on an externally generated clock signal (i.e., CLKIN). The creation of this externally generated clock signal will require additional devices, such as a Voltage-Controlled Oscillator.
In some situations, multiple pairs of two-phase, non-overlapping clock signals are desired. For example, a distributed DC-DC converter may be used in a high-current application (e.g., microprocessor power delivery). In this case, a number of simple converters will each receive a pair of two-phase, non-overlapping clock signals—and the pair of clock signals received by each converter will be shifted in phase as compared to the other converters.
FIG. 2
illustrates a known circuit
200
that generates three two-phase, non-overlapping clock signal pairs. Here, CLKIN propagates through a delay line having a number of non-inverting delay elements
210
. In this way, three offset versions of CLKIN are generated. Each version of CLKIN is provided to an independent circuit
100
that generates a single pair of two-phase, non-overlapping clock signals (i.e., CLK
1
A and CLK
1
B, CLK
2
A and CLK
2
B, or CLK
3
A and CLK
3
B). Note that each independent circuit
100
may operate as described with respect to FIG.
1
. The three pairs of non-overlapping clock signals can then be provided to a distributed DC-DC converter.
Note that the operation of the circuit
200
is dependent on an externally generated clock signal (i.e., CLKIN). As another approach, the delay line could be a sub-circuit of a ring oscillator, VCO, Delay-Locked Loop (DLL), or Phase-Locked Loop (PLL) that generates the clock signals to be provided to each circuit
100
. In that case, CLKIN would not be required unless there is a need for synchronization of the generated clocks to some external clock signal.
Another disadvantage is that a separate circuit
100
is needed to generate each pair of non-overlapping clock signals. Such an approach may require a large number of circuit elements, consume a significant amount of power, and/or occupy a large area in a microprocessor die.


REFERENCES:
patent: 4236121 (1980-11-01), Senturia
patent: 4417158 (1983-11-01), Ito et al.
patent: 4560954 (1985-12-01), Leach
patent: 5086236 (1992-02-01), Feemster
patent: 5357217 (1994-10-01), Marchesi et al.
patent: 5444405 (1995-08-01), Truong et al.
patent: 5818276 (1998-10-01), Garrity et al.

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