Non-monotonic dynamic exclusive-OR/NOR gate circuit

Details Non-monotonic dynamic exclusive-OR/NOR gate circuit Non-monotonic dynamic exclusive-OR/NOR gate circuit

2000-05-25

2002-01-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S113000

Reexamination Certificate

active

06335639

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to logic gates used in integrated circuits. More specifically, the invention relates to the structure of a logic gate which implements an exclusive-OR/NOR function.
2. Background Art
A majority of modem large-scale integrated circuits, such as microprocessors and memories, comprise logic gates that use p-channel and n-channel field-effect transistors (FET) in a complementary fashion to perform different logic functions. To reduce the area occupied by the logic gates on a single chip, it is usually desirable to construct the logic gates from the barest minimum number of transistors possible.
FIG. 1
illustrates a logic gate
2
which is based on complementary metal-oxide semiconductor (MOS) technology, or simply CMOS technology. The CMOS logic gate
2
includes a pre-charge device
4
, an evaluation device
6
, and a logic network
8
. The pre-charge device
4
is a p-channel MOS (PMOS) transistor, and the evaluation device
6
is an n-channel MOS (NMOS) transistor. The gate terminals of the PMOS transistor
4
and the NMOS transistor
6
are connected to a clock signal (CLK). The drain terminal of the PMOS transistor
4
is connected to a node
7
of the logic network
8
, and the source terminal of the NMOS transistor
6
is connected to a node
9
of the logic network
8
. The source terminal of the PMOS transistor
4
is connected to a supply voltage signal (V
DD
), and the drain terminal of the NMOS transistor
6
is connected to ground signal (GND).
The logic network
8
is designed such that the correct function is produced at the output (OUT) of the inverter
10
. Without the presence of the inverter
10
, the CMOS logic gate
2
would implement an exclusive-NOR (XNOR) function. The logic network
8
is made of NMOS transistors
12
-
18
. The source terminals of the NMOS transistors
12
,
14
are connected to the drain terminal of the PMOS transistor
4
, and the drain terminals of the NMOS transistors
12
,
14
are connected to the source terminals of the NMOS transistors
16
,
18
, respectively The drain terminals of the NMOS transistors
16
,
18
are connected to the source terminal of the NMOS transistor
6
. The gate terminals of the NMOS transistors
12
,
18
receive input signals A and B, respectively. The gate terminals of the NMOS transistors
16
,
14
receive input signals {overscore (A)} and {overscore (B)}, respectively, where input signal {overscore (A)} is the complement of input signal A, and input signal {overscore (B)} is the complement of input signal B. The logic gate
2
requires additional circuitry (not shown) for producing the complement input signals {overscore (A)} and {overscore (B)}. This additional circuitry increases the size and complexity of the logic gate
2
.
SUMMARY OF THE INVENTION
One aspect of the invention is a logic gate for producing an output signal representing a logical operation of a first logic signal and a second logic signal. The logic gate comprises a first input which receives the first logic signal and a second input which receives the second logic signal. The logic gate further includes a first transistor, a second transistor, and an evaluation node which is connected to a pre-charge device. The first transistor has a first terminal coupled to the first input, a second terminal coupled to the evaluation node, and a third terminal coupled to the second input. The second transistor has a first terminal coupled to the second input, a second terminal coupled to the evaluation node, and a third terminal coupled to the first input. A change in either of the logic signals triggers the logic gate, and a change in both of the logic signals within a predetermined time period results in the logic signals simultaneously canceling each other out.


REFERENCES:
patent: 4767947 (1988-08-01), Shah
patent: 5399921 (1995-03-01), Dobbelaere
patent: 5736868 (1998-04-01), Kim et al.
patent: 5861762 (1999-01-01), Sutherland

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