Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-08-10
2002-08-06
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S687000
Reexamination Certificate
active
06429122
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to microelectronics fabrications and, in particular, to methods of forming conducting interconnect structures that are protected from diffusion of chemical species into and out of surrounding materials.
2. Description of the Related Art
As the structures comprising integrated microelectronic circuitry continue to decrease in size, the conducting interconnects between them decrease in size as well. Smaller conducting interconnects must be composed of materials with higher conductivity and greater mechanical integrity, which presently favors the use of copper (Cu), with twice the conductivity of aluminum and three times the conductivity of tungsten, as the material of choice. Unfortunately, copper has been found to contaminate many of the materials used in integrated circuit fabrications, so special care must be taken to keep it from migrating into surrounding regions.
Several methods have been developed to provide containment of copper deposited as conducting leads and interconnects. Chief among these is the prior formation of diffusion barriers and liner layers within the trenches and vias into which the copper is subsequently deposited. Copper inlays surrounded by layers of other metals and their compounds such as tungsten, tantalum, molybdenum and titanium nitride, are called copper damascene structures.
Although the damascene process is an important step forward in forming viable copper interconnects, it does have problems associated with it which must be addressed. The barrier layer may itself be subject to degradation from surrounding materials. The barrier layer may not adhere well to the copper or to the surrounding material. The barrier layer may adversely affect the contact between the interconnect and other conducting layers. The barrier layer may be difficult to fabricate with the requisite thinness in small trenches and vias. With regard to the affect of surrounding materials on the barrier layer, it should be pointed out that fluorinated materials such as amorphous fluorinated carbon, PTFE, fluorinated polyimide and fluorinated silicon dioxide are presently being used as interlayer dielectrics because their low dielectric constants (low-k) tend to reduce parasitic capacitance between neighboring conducting lines and vias. When fluorinated materials are subjected to high temperature processing (above 3000° C.), which is quite common in the complex fabrication schemes of integrated microelectronic circuitry, the fluorine tends to out-diffuse into previously deposited metallic barrier layers and form metallic fluoride compounds (eg., fluorine diffusing into tantalum forms tantalum fluoride, TaF). These compounds degrade the adhesion and integrity of the metallic layers and lead to their delamination.
Several of the aforementioned problems have been addressed by recent inventions. Nguyen et al (U.S. Pat. No. 5,904,565) teach a damascene process which allows a direct copper to copper connection between vias on different but contiguous levels of an integrated circuit. Their method involves removal of the bottom portion of the barrier layer with an anisotropic etch, so that the copper inlay is put into direct contact with the upper portion of the copper inlay on the level below it. Teong (U.S. Pat. No. 5,693,563) teaches an alternative method for solving the same double level contact problem, wherein two barrier layers are used to enhance the connection properties. Iguchi et al (U.S. Pat. No. 5,744,394) teach a method for interconnecting a series of transistors in an integrated circuit fabrication wherein the interconnection layer is connected to the transistors through a barrier layer which can be formed of any one of a number of metals or their compounds. Stolmeijer (U.S. Pat. No. 5,834,845) teaches a method for fabricating a multilevel interconnect structure composed of similar patterned metal layers as building blocks. These blocks are then connected by tungsten or aluminum plugs surrounded by titanium (Ti) or titanium nitride (TiN) barrier layers. Jain et al teach a method of improving the fabrication process of dual damascene structures by coating the devices with an anti-reflective material. This coating then enhances the photolithography process and also acts a a barrier layer for the copper interconnects.
Although each of the above cited inventions teach applications and improvements of the damascene process, they fail to address certain specific difficulties associated with the intrinsic nature of the process. In its various embodiments, the present invention differs from those cited above by addressing the following issues: the degradation of metallic barrier layers by the out-diffusion of fluorine from fluorinated dielectrics into those layers, the difficulty of using metallic barrier layers to conformally line trenches and vias of dimension less than 0.15 microns and the use of a novel class of non-conducting barrier layers to improve the adhesion of metallic barrier layers and copper inlays to trench and via sidewalls when the dimensions of these formations are less than 0.15 microns.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a method for preventing the out-diffusion of fluorine from fluorinated dielectric materials into the metallic barrier layers such as those that characterize damascene interconnects.
A second object of this invention is to provide a method for preventing the out-diffusion of fluorine from fluorinated dielectric materials directly into conducting materials that may fill trenches and vias not lined with metallic barrier layers.
A third object of this invention is to provide a method for preventing conducting materials, such as copper, deposited in trenches and vias, from diffusing into surrounding dielectric materials.
A fourth object of this invention is to provide a method for preventing conducting materials, such as copper, sputtered onto the sidewalls of trenches and vias during etching, from diffusing into surrounding dielectric materials.
A fifth object of this invention is to provide a method of conformally lining trenches and vias whose aspect ratios are continually increasing with each technology generation, thus allowing the continued use and benefits of copper interconnects for devices of the 0.15 micron generation and beyond.
A sixth object of this invention is to provide a method for forming a lining layer whose low-k dielectric properties help to reduce the problems associated with parasitic capacitance between conducting interconnects and other neighboring structures.
A seventh object of this invention is to provide a method for forming a liner layer with improved adhesion properties between conductors and porous dielectrics.
An eighth object of this invention is to provide a method for forming a chemically inert spacer layer that protects surrounding materials from the effects of etches and post etch solvent stripping processes.
In one embodiment of the present invention these objects will be achieved by the chemical vapor deposition (CVD) or physical vapor deposition (PVD) of a non-metallic spacer layer interposed between the surrounding fluorinated dielectric material and a metallic barrier layer.
In another embodiment of the present invention particularly suited to trenches and vias whose minimum dimensions are less than 0.25 microns, these objects will be achieved by the plasma-enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD) of a barrier layer composed of one of a class of low dielectric constant (low-k) carbon-based amorphous materials that can be deposited conformally to a thickness of 15 nanometers or less. For example, Teflon is such a low-k material (1.9≦k≦2.1) that adheres well to other dielectric materials. Its adhesion to copper can even be enhanced by depositing it over a prior layer of polyaniline or by modifying its surface to a hydrophobic condition. Such amorphous carbon-based materials will prevent the out-diffusion of copper from the conducting intercon
Chooi Simon
Gupta Subhash
Hong Sangki
Zhou Mei-Sheng
Chartered Semiconductor Manufacturing Ltd
Le Dung A
Nelms David
Pike Rosemary L. S.
Saile George O.
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