Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-11-19
2000-01-18
Palys, Joseph E.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 34, G06F 1578
Patent
active
060165553
ABSTRACT:
A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
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Deao Douglas E.
Seshan Natarajan
Donaldson Richard L.
Laws Gerald E.
Marshall, Jr. Robert D.
Omar Omar A.
Palys Joseph E.
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