Non-imprinting memory with high speed erase

Details Non-imprinting memory with high speed erase Non-imprinting memory with high speed erase

2008-05-27

2008-05-27

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S185040, C365S189050

Reexamination Certificate

active

11402696

ABSTRACT:
A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state. A state machine tracks polarity state of the first true/complement data so as to control whether a same polarity or opposite polarity state read operation is performed by the read/write circuit.

REFERENCES:
patent: 4864544 (1989-09-01), Spak et al.
patent: 5146225 (1992-09-01), Theus
patent: 6490646 (2002-12-01), Leydier
patent: 2007/0150887 (2007-06-01), Shapiro

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