Non-fenced list DMA command mechanism

Details Non-fenced list DMA command mechanism Non-fenced list DMA command mechanism

2007-04-10

2007-04-10

Huynh, Kim (Department: 2181)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C710S022000, C710S024000, C710S308000

Reexamination Certificate

active

10631542

ABSTRACT:
A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.

REFERENCES:
patent: 5619723 (1997-04-01), Jones et al.
patent: 6076158 (2000-06-01), Sites et al.
patent: 6427201 (2002-07-01), Ohba
patent: 2004/0187122 (2004-09-01), Gosalia et al.
patent: 2004/0187135 (2004-09-01), Pronovost et al.

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