Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-11-02
1997-04-01
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
216 41, 438624, 438627, 438633, 438636, 438637, H01L 2144, H01L 2148
Patent
active
056165196
ABSTRACT:
A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow photoresist plugs, and filling the spaces between photoresist plugs with a planarizing layer of a composite dielectric, which includes a spin on glass layer. Removal of the photoresist plug results in the creation of a narrow via hole. The composite dielectric was deposited by initially using a non-porous, silicon oxide layer, followed by the planarizing spin on glass layer. Therefore metal via fills will interface the non-porous, silicon oxide layer.
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Bowers Jr. Charles L.
Chartered Semiconductor Manufacturing Pte Ltd.
Gurley Lynne A.
Saile George O.
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