Non-epitaxial CMOS structures and processors

Details Non-epitaxial CMOS structures and processors Non-epitaxial CMOS structures and processors

1995-01-05

1996-03-19

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257372, 257373, 257376, 257394, 257773, H01L 2976

Patent

active

055005489

ABSTRACT:
An integrated circuit device (10) is provided that comprises an P-FET (12) and an N-FET (14) formed on a semiconductor substrate (32). The P-FET (12) is formed in an n- tank (46). The source (18) and back-gate contact (22) of the P-FET (12) are connected to the V.sub.DD supply voltage. A current sink region (50) is formed in contact with the bulk semiconductor substrate (32). Periodic back-gate contacts (30) and (52) are made to the current sink region (50). The source (26) of N-FET (14) is also connected to the back-gate contacts (30) and (52). The current sink region (50) provides a low resistance path for charge within the substrate (32) to paths to the supply voltage V.sub.SS. This low resistance path prevents voltage from building up in the substrate (32) and thereby prevents latchup from occurring.

REFERENCES:
patent: 5003362 (1991-03-01), Lee et al.

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