Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-09
2002-09-10
Flynn, Nathan J. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C257S048000
Reexamination Certificate
active
06449748
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices. More particularly, the present invention relates to methods for detecting die crack problems in packaged integrated circuits.
Integrated circuits (ICs) are typically formed on a wafer of semiconductor material that is subsequently cut into individual dies for which are then packaged for use in their intended application. Packaged ICs are sometimes referred to as computer “chips.” A main concern of semiconductor device fabricators is the reliability of the chips that are shipped to customers. One problem commonly encountered in chips is failure of their circuits due to cracking of the die on which an IC is formed.
One way that semiconductor device fabricators have attempted to control die crack problems is by taking steps to detect them at the process and packaging development stage of device fabrication. During process and packaging development, test dies are subjected to procedures and their associated forces proposed to be used in the fabrication of production chips. In order to test for die cracking problems, guard rings are formed in the test dies for a given process and package. These guard rings are composed of conductive lines between pads formed at the perimeter of the die. A crack in the die results in a break in the conductive line that is detected when a signal applied at a pad at one end of the line is not received by the pad at the other end of the line.
FIG. 1
shows an example of one implementation of guard rings used to detect die crack problems in process and packaging test dies. The test die
100
is shown in simplified form in order to focus on the guard ring aspect of the die
100
. The die
100
includes a function circuit
102
surrounded by a number of input nodes (or “pins”)
104
and output nodes
106
at the perimeter of the die
100
. Also at the perimeter of the die is a guard ring, such as described above. Guard rings are composed of conductive lines, usually of metal, which are formed in one or more layers of a test die. For example the guard rings may be formed in a polysilicon layer, and/or a metal
1
layer, and/or a metal
2
layer, etc. Guard rings typically have between two and eight pads (more than two pads are used when the conductive lines are separated into segments which assists in localization of a crack in the die). In this example, the guard ring is divided into four segments
110
,
120
,
130
and
140
, each with pads
112
,
122
,
132
and
142
, respectively, at either end. Collectively, these segments form a ring around the perimeter of the die
100
.
A disconnect in a segment of the guard ring indicates a crack in that region of the die
100
. Thus, such guard rings are useful to determine whether or not particular processing or packaging protocol tends to produce die cracking, may be useful to modify or reject process and/or packaging steps that are shown to cause an unacceptable number of die cracks during process and package development. However, it is impractical to place guard rings in actual chips which are produced and sold to customers (production chips) due to the amount of space required on the chip and the additional processing for this additional circuitry. Therefore, such guard rings are not useful in identifying and localizing die cracks in production chips where problems may develop later.
The conventional procedure for identifying and localizing die crack problems in production chips is that the failing chips are returned to the manufacturer, and some or all of the packaging is removed in order to provide access for a visual inspection of the die. This destructive removal of packaging is a process know as “decapping.” Decapping procedures vary depending on the particular packaging used for the chip. For example, in the case of PBGA (Plastic Ball Grid Array) and PQFP (Plastic Quad Flat Pack) packages, decapping involves the removal of the polymeric resin covering the die, and in the case of a flip-chip package, decapping involves the removal of the heat spreader. Decapping is both a time consuming and expensive process and is ideally to be avoided.
Accordingly, it would be desirable if a method could be implemented to identify and localize die crack problem in production chips.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides a non-destructive method of detecting die crack problems in an integrated circuit. The method provides for testing for die crack problems in all chips and in many production chips without adding any extra circuitry or pads. In a preferred embodiment, the method takes advantage of an existing NAND gate tree structure at the perimeter of many conventional dies, for example, the LXA0372 die, manufactured by LSI Logic Corporation, Milpitas, Calif. The invention is also applicable to other logic gate structures that may exist or may be formed at the perimeter of dies.
The invention recognizes that this NAND gate tree structure may be used in order to identify and localize die cracks in finished chips, thereby providing a faster, more accurate and nondestructive way to test for die cracks in production chips. A typical NAND gate tree structure has the form of a cascade inverter chain. Since one end of the first NAND gate is tied to V
DD
, the output of each gate will alternate between low and high. Knowing the number of NAND gates in chain and the input provided to each NAND gate, the output for a properly functioning chain is determinable. If the output received is unexpected, it is an indication of die cracking in the chip. Moreover, by conducting a test pattern where a range, ideally the minimum combination necessary, of inputs is provided at each NAND gate and the output recorded, it is possible to localize the gate and or gates which are not responding properly and thereby localize the die crack.
Since, in a preferred embodiment, this test method requires no new circuitry in a conventional chip design, it is both low cost and efficient use of chip area. A test protocol including a cycle which provides the permutations of inputs to the NAND gates necessary to identify and localize die cracking may be provided to the customer together with the production chip. Thus, if a chip fails, the customer may run the test protocol in order to determine if the failure is due to die cracking rather than some problem with the chips's function circuits, and localize the die crack.
Generally, this method is not restricted to NAND gate tree structures. For example, the input nodes may include NOR logic gates, or a combination thereof. NAND gate tree structures are the preferred embodiment since they are already present in many chip designs.
In one aspect, the present invention provides a method of detecting die crack problems in an integrated circuit. The method involves providing an integrated circuit on a die having a logic gate tree structure around the perimeter of the die. The logic gate tree structure has a plurality of input nodes connected with logic gates and at least one output node. A pattern of voltage signals is applied at the plurality of input nodes, and voltage signals are determined at the at least one output node for the applied pattern of voltage signals. The voltage signals at the at least one output node provide an indication of whether or not there is a die crack.
In another aspect, the present invention provides a system for detecting die crack problems in an integrated circuit. The system includes an integrated circuit on a die having a logic gate tree structure around the perimeter of the die, said logic gate tree structure comprising a plurality of input nodes and at least one output node;
a computer-implemented protocol capable of controlling the application of a pattern of voltage signals at said plurality of input nodes, and determining voltage signals at said at least one output node for said applied pattern of voltage signals;
wherein the voltage signals at the at least one output node provide an indication of whether or not there is a die crack.
REFERENC
Beleno Lamberto
Hsuing Steve Kehchien
Jeng Edward Jewjing
Beyer Weaver & Thomas LLP
Flynn Nathan J.
Garbowsk Leigh
LSI Logic Corporation
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