Non-defect image and data transfer and storage methodology

Details Non-defect image and data transfer and storage methodology Non-defect image and data transfer and storage methodology

1999-02-09

2001-01-09

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C382S145000, C438S016000

Reexamination Certificate

active

06171874

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacturing of high performance semiconductor devices. More specifically, this invention relates to a method of capturing and storing non-defect image and data information. Even more specifically, this invention relates to a method of capturing and storing non-defect image and data with linkage information in a data management system.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continually increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects occurring during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect increases the cost of the remaining usable chips.
Each semiconductor chip requires numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. In order to etch metal lines, for example, a layer of photoresist is formed on the surface of the semiconductor chips and patterned by developing the photoresist and washing away the unwanted portion of the photoresist. Because the metal lines and other metal structures have “critical” dimensions, that is, dimensions that can affect the performance of the semiconductor chip, the process of forming the photoresist pattern for each layer is examined during the manufacturing process. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits.
In the course of modern semiconductor manufacturing, semiconductor wafers are routinely inspected using “scanning” tools to find defects. The scanning tool determines the location and other information concerning defects that are caught and this information is stored in a data file for later recapture and inspection of any of the defects. These data files are stored in a relational database that has the ability to generate wafer maps with defects shown in their relative positions. The data database typically has the ability to send these wafer map files to various review tools within the manufacturing plant. This is very useful as it allows for re-inspection on various after-scan inspection tools within the manufacturing plant. These inspection tools include Optical Microscopes and Scanning Electron Microscopes (SEMs) that allow for classification of the defects. Images taken on the various after-scan inspection tools can be linked by linkage data to the defect on a wafer map and reviewed at a workstation at an engineer's or technician's convenience.
Wafers are also inspected on various microscopes and SEM's without the benefit of first being scanned and thus no wafer map file can be generated for these type inspections. These types of inspections are the various after DIs (Develop Inspections) and/or after etch inspections, as well as CD (critical dimension) monitoring, which routinely occur during the manufacturing process. These “views” and their locations, once inspected, are either captured on a printout or discarded.
FIG. 1
shows a typical prior art inspection methodology. A wafer lot is started through a manufacturing process, as indicated at
100
. The first layer of each wafer of the wafer lot is subjected to a first process,
102
. After the first process, a selected number of wafers are subjected to an ADI (after develop inspection) at
104
. The after develop inspection is done on various microscopes and/or SEMs by an operator. The operator performs the various DI (develop inspections) and/or after etch inspections, as well as performing CD (critical dimension) monitoring of selected features on the wafer. The operator has the capability to capture an image
106
of one of the features if there is an anomaly to one of the features that is of interest. The operator determines at
108
if the wafers should be further processed. If the operator determines that the wafers should not be further processed, the wafers are reworked at
110
. If the operator determines that the wafers are in a condition for further processing, the layer just processed on the wafers is inspected for defects, at
112
. The wafers are typically inspected on various scanning tools that identify defects. The defect data is stored
114
in a data file along with position data in a DMS (data management system)
116
. It is determined at
118
if a wafer map exists for the wafer. If a wafer map exists, the defect data is added to the existing wafer map, at
120
. If a wafer map does not exist, a wafer map is created at
122
. After the layer is inspected at
112
, it is determined if the layer just inspected is the last layer, at
124
. If it is determined at
124
that the layer just inspected is not the last layer, the wafers are sent to the next process at
126
and the wafers are returned to the process at
104
. If it is determined at
124
that the layer just inspected is the last layer, the process is finished
128
.
It has been increasingly noted that semiconductor devices have failures associated with faulty critical dimensions, some of which in turn have been associated with faulty photoresist development or etch processes. However, because the data concerning the critical dimensions, photoresist development or the etch process have either not been kept or, if they have been kept, they can not be linked to either a particular lot, a particular wafer, a particular layer or a particular xy position.
Therefore, what is needed is a method of transferring the image file and related data from a review tool, such as an SEM, ADI inspection station, Tilt SEM, etc., to a defect management station. The review tool would generate a small file containing operator generated information, for example, ProductID, LotID, WaferID, LayerID, etc., and the tool would generate machine generated information, such as, x location, y location, path to image file, etc. The defect management system would then, based on previous knowledge of the product, such as, for example, die pitch and placement, either generate a new wafer map for the particular Lot/Wafer/Layer or append the current map, if it exists, and send the image file to its own image server.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are attained by a method of manufacturing high performance semiconductor integrated devices in which non-defect images, image data and linkage data for the nondefect images are stored in a database that is available for later retrieval.
In accordance with an aspect of the invention, at least one inspection wafer is selected from a lot of semiconductor wafers and non-defect anomalies are captured and stored and added to a wafer map.
In another aspect of the invention, the layer on the lot of semiconductor wafers is then inspected for defects and the defect information is added to the wafer map.
The method of the present inve

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