Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2007-12-11
2007-12-11
Smith, Bradley K. (Department: 2891)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C257SE21545
Reexamination Certificate
active
11099339
ABSTRACT:
A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
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patent: WO 01/41199 (2001-06-01), None
Achuthan Krishnashree
Foster Christopher M.
Kim Unsoon
Kinoshita Hiroyuki
Raeder Christopher H.
Smith Bradley K.
Spansion LLC
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