Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
1998-08-06
2001-07-03
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S014000, C324S455000
Reexamination Certificate
active
06255128
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a non-contact method for determining the presence of a contaminant in a semiconductor device and, more specifically, to a non-contact method for determining donor atom contamination in a p-type silicon and acceptor atom contamination in an n-type silicon.
BACKGROUND OF THE INVENTION
The ongoing trends toward larger wafers, shrinking line widths, and ever thinner oxides are making tight in-line monitoring of wafer cleanliness and uniformity even more critical to semiconductor manufacturers. Contaminants can be any form of matter that causes unintentional changes in electrical properties of semiconductor devices. Some common contaminants include particles, atomic-ionic-molecular defects, and heavy metals.
The fabrication of complimentary metal oxide semiconductor (CMOS) devices involves numerous distinct manufacturing process steps. Device contamination, during any of these processes, poses a serious quality control problem and when severe, may necessitate that the devices be scrapped. To monitor contamination that occurs during the manufacturing process, manufacturers have developed tests that attempt to monitor contamination in the semiconductor device.
A measurement of electrically active contamination may be accomplished using a resistivity test. This is often done through the use of a tool having four probes that actually touch the top of the semiconductor wafer, where the tool measures the resistivity between the probes. These measurement probes themselves, however, tend to become contaminated from their contact with the surface and may therefore distort the measurements. Additionally, sensitivity also may be a problem, since electrically active contamination concentrations well below the resistivity measurement capability of the tool can cause performance degradation in the device under test.
Another popular method of measuring the free charges in the semiconductor device is the use of secondary ion mass spectroscopy (SIMS). The SIMS technique bombards the surface of the device under test with high energy charged particles in a “sputtering” fashion. These ions penetrate into the device, to a depth that is a function of their energy level, and excite a secondary ion emission from the device that is proportional to a contamination concentration level. The SIMS then measures the type and concentration of this free charge contamination. However, SIMS suffers from the severe limitation in that it measures concentration levels down to only about 5.0E14 atoms/ml for phosphorous (n-type). Therefore, contaminant concentrations below this level in semiconductor devices are not detected and may still cause serious performance problems. Additionally, the time required for the SIMS measurement process is a function of the target concentration level and may take days to determine the lower levels of contamination.
In summary, these measurement techniques typically require long periods of time to apply and do not have the measurement sensitivity to detect low contaminant concentration levels. Therefore, the information obtained from these tests is not available or detectable at the desired time during the fabrication process. This generally forces the testing to be done after the device has been fully fabricated and the majority of the manufacturing costs have been incurred. Moreover, it is not assured that trace amounts of contaminants will be detected. Additionally, since testing is performed on completed devices, as contrasted with devices that are still in the fabrication process, it is often difficult to determine the exact source or location of the contamination.
Accordingly, what is needed in the art is a way to quickly measure low levels of electrically active contaminants within the semiconductor device.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a non-contact method for determining whether a contaminant is present in a semiconductor wafer having a substrate/dielectric interface formed thereon. In one advantageous embodiment, the method comprises field inducing a junction in equilibrium inversion in the semiconductor wafer device. A conventional corona source may be used to induce the junction to equilibrium inversion. This particular embodiment further includes forming a contaminant junction near the substrate/dielectric interface when the contaminant is present in the semiconductor wafer by adding charge and pulsing the junction out of equilibrium. A surface voltage measurement, which may be taken with a Kelvin probe, is obtained by measuring a change in a surface voltage as a function of time. The method further includes determining whether the contaminant is present in the semiconductor wafer from the change in the surface voltage. When the contaminant is present in the device, the change in the surface voltage is insubstantial. This insubstantial change is in stark contrast to the change in surface voltage that occurs in a non-contaminated device. The data obtained from these surface voltages can be plotted with conventional devices to yield the change in surface voltage with respect to time.
Thus, one aspect oft the present invention provides a non-contact method for easily determining whether a contaminant is present in the device early in the semiconductor devices formation. Additionally, the present invention also provides a method that can D readily detect low levels of contamination that has been previously undetectable. Due to the sensitivity and accuracy of this method and the ease with which it can be conducted, substantial fabrication downtime, which is prevalent in present measuring processes, can be saved, thereby lowering the fabrication costs of the semiconductor device. Furthermore, the present method can be used to more closely monitor the cleanliness of the furnaces, which are often a source of contaminates in the semiconductor manufacturing process.
In another embodiment, the formation of the contaminant junction inhibits a formation of a deep depletion region within the semiconductor device. It is believed that the contaminant forms (contaminant skin, which in turn forms a pn junction at or near the substrate/dielectric interface because of the readily available source of either electrons or positive charge associated with the contaminant. The type of pn junction that forms depends on the type of contaminant that is present in the semiconductor device. Most often, the contaminant is a dopant material that is opposite to the dopant with which the device is doped. For example, if the intended dopant is a p-type of dopant, such as Boron, then the contaminant may be an n-type of dopant, such as phosphorous. In such instances, an n-type contaminant junction is formed. Alternatively, the intended dopant may be an n-type dopant and the contaminant dopant may be a p-type dopant, which would form a p-type of contaminant junction. It is believed that the formation of this pn junction prevents deep depletion from occurring in the device.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those who are stilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those who are skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 4812756 (1989-03-01), Curtis et al.
patent: 5216362 (1993-06-01), Verkuil
patent: 6011404 (2000-01-01), Ma et al.
O'Mara et al, Handbook of Semiconductor Silicon Technology, 1990, Noyes Publications, New York,
Chacon Carlos M.
Roy Pradip K.
Lucent Technologies - Inc.
Meier Stephen D.
Vockrodt Jeff
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