Non-clocked static memory cell

Details Non-clocked static memory cell Non-clocked static memory cell

1987-02-13

1989-07-04

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 36518905, 365190, G11C 700, G11C 1140

Patent

active

048456764

ABSTRACT:
A static memory cell comprising a pair of cross-coupled transistors and a bit line driver/isolation stage configured as an inverter disposed between one node of the cross-coupled transistors and a read-select transistor. The cell is accessed through a bus which includes a read bit line and a write bit line, the word line being divided into a write word line and a read word line.

REFERENCES:
patent: 4262340 (1981-04-01), Sasaki et al.
patent: 4380055 (1983-04-01), Larson
patent: 4499558 (1985-02-01), Mazin et al.
patent: 4527255 (1985-07-01), Keshtbod
patent: 4653025 (1987-03-01), Minato et al.
patent: 4654823 (1987-03-01), Charransol et al.
R. H. Linton et al., "Low-Power FET Storage Cell," IBM Technical Disclosure Bulletin, vol. 17, No. 11, Apr. 1975, pp. 3338-3339.
U. Baitinger et al., "Monolithic Storage Cell with FET's," IMB Technical Disclosure Bulletin, vol. 14, No. 12, May 1972, pp. 3640-3641.

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