Patent
1995-12-11
1999-02-09
Lee, Thomas C.
395840, G06F 9312
Patent
active
058706259
ABSTRACT:
A computer system is disclosed which has a plurality of masters, such as a processor, a cache memory or an I/O device controller. Read response time from the main memory is minimized by a read-from-write scheme which gives priority to read commands. If a read command is to access data with the same address of a previously issued but pending write command in the buffer of a memory controller, then the read and write commands are combined and the read/write command is given priority over each other pending read or write command. To further reduce mean read response time, the data to be written to the main memory is transferred directly from the buffer to the master which issued the read command contemporaneously with the execution of the write command on the main memory.
REFERENCES:
patent: 3771137 (1973-11-01), Barner et al.
patent: 5008808 (1991-04-01), Fries et al.
patent: 5224214 (1993-06-01), Rosich
patent: 5333276 (1994-07-01), Solari
patent: 5379379 (1995-01-01), Becker et al.
patent: 5404480 (1995-04-01), Suzuki
patent: 5517660 (1996-05-01), Rosich
patent: 5524220 (1996-06-01), Verma et al.
patent: 5524235 (1996-06-01), Larson et al.
patent: 5553265 (1996-09-01), Abato et al.
patent: 5627993 (1997-05-01), Abato et al.
Chan Cheng-Sheng
Pan Tienyo
Industrial Technology Research Institute
Lee Thomas C.
Ton David
LandOfFree
Non-blocking memory write/read mechanism by combining two pendin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-blocking memory write/read mechanism by combining two pendin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-blocking memory write/read mechanism by combining two pendin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1959087