Non-blocking delayed clocking system for domino logic

Details Non-blocking delayed clocking system for domino logic Non-blocking delayed clocking system for domino logic

1997-06-30

2000-01-25

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 93, H03K 19096

Patent

active

060182547

ABSTRACT:
A non-blocking multiple-phase clocking system for use with domino-type dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. The clocking system provides a first clock phase to the first dynamic logic gate, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives. This adjustment of the clock phases maximizes the logic evaluation speed of the dynamic logic circuit.

REFERENCES:
patent: 5434520 (1995-07-01), Yetter et al.
patent: 5504441 (1996-04-01), Sigal
patent: 5541536 (1996-07-01), Rajivan
patent: 5880609 (1999-03-01), Klass et al.
Wang, J.S., et al., "Novel Dynamic CMOS Logic Free From Problems of Charge Sharing and Clock Skew," International Journal of Electronics, vol. 66, No. 5, pp. 679-395, May 1989.
Gaddis, N.B. et al., "A 56-Entry Instruction Reorder Buffer", 1996 IEEE International Solid-State Circuits Conference, pp. 212-213, (1996).
Partovi, H. et al., "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements", ISSCC Slide Supplement, p. 104, (1996).
Shoji, Masakazu, CMOS Digital Circuit Technology, Prentice Hall, NJ, pp. 216-217, (1988).
Yuan, Jiren et al., "A True Single-Phase-Clock Dynamic CMOS Circuit Technique", IEEE Journal Of Solid-State Circuits, vol. 22, Oct. 1987, pp. 899-901.
Yuan, Jiren et al., "High-Speed CMOS Circuit Technique", IEEE Journal Of Solid-State Circuits, vol. 24., Feb. 1989, pp. 62-70.

Affiliated with

Also associated with

Rating

Non-blocking delayed clocking system for domino logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-blocking delayed clocking system for domino logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-blocking delayed clocking system for domino logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2318209