Non-aligned double word access in word addressable memory

Details Non-aligned double word access in word addressable memory Non-aligned double word access in word addressable memory

1999-08-23

2003-05-27

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Incrementing, decrementing, or shifting circuitry

C711S220000, C711S211000, C711S005000

Reexamination Certificate

active

06571327

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to Very Large Scale Circuit Integration (VLSI) circuit memories in general and more particularly to the non-aligned word recall aspects of word addressable memories.
BACKGROUND OF THE INVENTION
Digital Signal Processors (DSP's) consist of a number of components of which the principal unit is a computation unit (CU). The CU consists of a number of sub-units which are capable of performing operations on operands (numbers). Examples of these units include a multiplier (multiplies operands), an arithmetic logic unit (ALU) (adds, subtracts and performs logic operations) and a barrel shifter (BS) (increases or decreases numbers by an order of magnitude).
In order to supply the above-mentioned units of the CU with operands the DSP supplies an address corresponding to a required operand contained within a memory array.
Memories contain many numbers or operands one or more of which may need to be accessible to the CU. More particularly, as is increasingly the case today, when parallel CU's are employed, two or more operands may be required to be supplied simultaneously. For example, one multiplier requires two operands for its operation, whereas two multipliers require four operands. In practice, when two or more operands are required by a CU (or by a number of CU's which are joined together in parallel) at the same time, there is a restriction, due to the way that conventional memories are structured, on where these operands may be drawn from and in which fashion they may be withdrawn from within the memory array. Attempts have been made to overcome these limitations and an example of one such attempt follows. These methods of overcoming the limitations are very expensive due to, amongst other things, the increased area of silicon wafer required. Alternatively, certain memory transactions can be restricted, which affects the overall performance of the DSP.
FIG. 1
, which is now referred to herein, shows an example of a standard memory architecture attached to multiple CU's,
1
, contained in DSP
3
in accordance with the prior art. Standard memory array
2
is made up of rows
4
and there are a fixed number of word storage areas
6
in each row. The structure is similar to pigeonholes in a post office sorting rack, each pigeonhole or word storage area
6
being designated by an address containing a word
6
. The number of words placed in each row is dependent on many factors including memory speed required and area of the memory array required. The exemplary standard memory
2
, shown in
FIG. 1
has eight memory cells per row.
FIG. 2A
which is a flow chart illustration of the steps required to retrieve a word from memory
2
is now referred to herein. In the center of memory
2
, there is a row decoder (RDEC),
8
. To access memory
2
, RDEC
8
selects a row
4
(step
16
) in accordance with an address signal sent by DSP
3
(step
14
). The selected row
4
is routed to another unit within memory
2
known as a Word Select (WS) decoder
12
. WS decoder
12
comprises a series of “AND” gates
22
A-
22
H. WS decoder
12
selects one word from a selected word storage area
6
(step
18
).
Each “AND” gate
22
A-
22
H represents a word on a row
4
of memory array
2
and receives a signal (not shown) from DSP
3
, indicating that it should be selected. For example, “AND” gate
22
A represents word
6
corresponding to the binary number 000 (0) and gate
22
B represents word
6
corresponding to the binary number 001 (1). It should be noted that only the three Least Significant Bits (LSB's) of a DSP address are required in order to differentiate between, for example, eight words
6
on a row
4
of memory array
2
, in this particular example. If there were more words per row in memory array
2
, more LSB's would be required to differentiate the words. In general, 2
n
is the size of memory accessible by n bits. Thus a 64K memory requires 16 bits to access it and a 32K memory requires 15 bits.
WS decoder
12
may optionally contain a double word selector
19
which allows the selection of two words in a row
4
in limited circumstances. The double word selection feature which will be described further hereinbelow is an example of an attempt to overcome the limitations of conventional memories as mentioned hereinabove and described further hereinbelow.
The address which is provided by the DSP
3
or any other processor controls the RDEC
8
and WS unit
12
. A single address allows only one word from the memory
2
to be selected. In other words, only one RDEC
8
is activated per single address.
As mentioned above, there is often a need to bring two operands (words
6
) simultaneously from the memory
2
. Utilizing the memory
2
shown in
FIG. 1
, two distinct cases can be differentiated. The first case is the one in which the two words are in the same row
4
(aligned words) of memory
2
and the second case is the one in which the two words are located in two different rows
4
(non-aligned words) of memory
2
, the different rows being opposite to each other (i.e if one is odd the other is even). In the former case, the two aligned words may be selected almost in the same manner as a single word. The selected row (according to one RDEC
8
) is routed to the WS decoder
12
area where two words are selected therefrom rather than one. Selection of two non-aligned words is not achievable in a conventional memory array
2
, such as that illustrated in
FIG. 1
, without architectural changes to the memory. For example, the use of a dual port memory facilitates the selection of two non-aligned words. When it is desired to achieve the selection of two words utilizing a conventional memory, a double word selector
19
is installed in WS
12
, as mentioned hereinabove. The double word selector
19
is only capable of facilitating the selection of two aligned words and its installation in the memory involves extra expense.
As an example,
FIG. 1
includes double word selector
19
which comprises a series of multiplexers (Mux)
20
A-
20
H each connected to the pair of adjacent “AND” gates
22
A-
22
H and to the corresponding “AND” gate of WS
12
. Each “AND” gate
22
A-
22
H represents a word on a row
4
of memory array
2
. Thus, in the present example, there are eight “AND” gates
22
A-
22
H. Each Mux, apart from the first and last in the row of eight, receives three signals known as a double word minus 1 (DW−1), double word plus one (DW+1) and current signal. These signals from DSP
3
indicate to a Mux whether to accept the signal from the previous adjacent “AND” gate, the current “AND” gate or the adjacent “AND” gate ahead of it. Thus, two aligned words may be simultaneously selected. The first Mux does not accept a DW−1 signal, as there is no “AND” gate previous to it. The last Mux does not accept a DW+1 signal, as there is no “AND” gate after it. This serves to emphasize that it is possible to select only aligned words (on the same row). Further, it is apparent from the structure that only second or double words adjacent to each other are allowed.
Reference is now made to
FIG. 2B
which is a flow chart illustration of the process of selecting a double word when a double word selector
19
is installed in a standard memory. Similar reference numerals to those in previous figures refer to similar operations and will not be described further.
The operation of
FIG. 2B
begins with steps
14
and
16
whereby DSP
3
generates an address and row decoder
8
selects a row
4
in memory array
2
as described previously. The Mux corresponding to the selected word then allows that word to be selected (step
18
), utilizing the “current ” signal from DSP
3
as is the usual case when no double word selector
19
is installed. The “current” signal is required as there are alternatives (not present) available when a double word selector
19
is installed necessitating a positive selection of the current signal.
For
FIG. 2B
, however, when a “double word ” is selected (step
30
) DSP

Affiliated with

Also associated with

Rating

Non-aligned double word access in word addressable memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-aligned double word access in word addressable memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-aligned double word access in word addressable memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3064549