Non-address transition detection memory with improved access tim

Details Non-address transition detection memory with improved access tim Non-address transition detection memory with improved access tim

1989-04-27

1990-10-16

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365208, G11C 700

Patent

active

049640836

ABSTRACT:
A memory which senses output signals from a selected memory cell during a read cycle using a non-address transition detection apparatus. The memory has a plurality of memory cells which provide signals to a pair of bit lines when selected. An input circuit drives word lines and select a bit line pair of a memory cell located at the intersection of a selected word line and a selected bit line pair. The memory cell outputs bit line signals which are sensed by a combination of a differential amplifier, a level shifter, and a transconductance amplifier, and are thereafter output and presented externally at a logic state representative of a differential current at outputs of the transconductance amplifier. The combination sensing apparatus and a method for constructing such an apparatus decrease access time significantly over a prior art memory using address transition detection.

REFERENCES:
patent: 4485319 (1984-11-01), Davies et al.
patent: 4583203 (1986-04-01), Monk
patent: 4910713 (1990-03-01), Madden et al.

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