Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-09-28
2002-02-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S105000
Reexamination Certificate
active
06346831
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to circuits and, more particularly, to domino circuits.
2. Background Art
Technology scaling combined with aggressive design practices have made high performance digital circuits more susceptible to deep submicron noise. Among various noise disturbances, one major concern is leakage current degradation, which can become substantial in sub-
1
V, 0.1 &mgr;m technologies. This is primarily because the reduced supply voltage and high speed requirements force designers to use low threshold voltage (Vt) transistors. Reducing threshold voltage, on the other hand, increases the leakage current exponentially. Large leakage current results in higher DC offsets at the inputs of wide domino circuits, degrading the noise tolerance. The term noise immunity refers to the degree to which a circuit is noise tolerant.
Wide-fanin gates are gates having numerous input ports. Wide-fanin gates are routinely employed on critical delay paths of high-performance datapaths, such as in a microprocessor, digital signal processor, or other semiconductor device. Dynamic/Domino logic techniques have been used to achieve substantially higher performance than are provided by static complementary metal oxide semiconductor (CMOS) technology for wide-fanin gates.
As an example,
FIG. 1
illustrates a conventional prior art wide-fanin OR domino gate or circuit
10
having a domino stage
12
and an output stage
14
joined by a node Q which carries a domino stage output signal. Domino stage
12
includes an evaluate network
16
, precharge and keeper p-channel metal oxide semiconductor field effect transistors (PMOSFET) M
2
and M
3
and an inverter
18
. Output stage
14
is illustrated as an inverter, but may be a dual function generator or other output stage. Evaluate network
16
includes eight n-channel metal oxide semiconductor field effect transistors (NMOSFET) M
1
-
0
. . . M
1
-
7
, the gates of which receive corresponding input signals Vin
0
. . . Vin
7
. A wide-fanin gate may have a greater or lesser number of inputs.
During a precharge phase, input signals Vin
0
. . . Vin
7
and a clock signal (Clk) are low (Vss). When Clk goes low, pull-up PMOSFET M
2
is turned ON and node Q is pulled high to a power supply node Vcc (sometimes called Vdd). As signal Q goes high, an inverter
18
turns on PMOSFET M
3
which keeps signal Q high after Clk transitions high and PMOSFET M
2
is off. During an evaluate phase, if each input remains low, Q remains high and the output signal Out at the output conductor
22
of output stage
14
remains low. If one or more of input signals Vin
0
. . . Vin
7
goes high, the corresponding NMOSFET(s) M
1
-
0
. . . M
1
-
7
is turned ON pulling signal Q low. When signal Q goes low, Out on conductor
22
goes high.
To improve noise tolerance, NMOSFETs M
1
-
0
. . . M
1
-
7
have a high Vt so that a greater noise voltage is required to turn on the transistor. However, this sacrifices pull-down speed. To enable the use of low Vt transistors for high speed, certain noise tolerance mechanisms have been proposed.
One such noise tolerant technique is illustrated in FIG.
2
. Referring to
FIG. 2
, a domino circuit
30
includes a domino stage
32
and an output stage
14
. Evaluate network
34
includes NMOSFET M
1
-
0
. . . M
1
-
7
, the gates of which receive corresponding input signals Vin
0
. . . Vin
7
. The sources of M
1
-
0
. . . M
1
-
7
are at a node X. A pull-up PMOSFET diode M
4
increases the source potential (node X) of evaluate network
34
. An NMOSFET M
5
isolates node X from ground during the evaluate stage. The Vt of an NMOSFET increases when it is reverse body biased, which occurs when the source voltage is greater than the body voltage. NMOSFET M
1
-
0
. . . M
1
-
7
have a grounded body. A reverse body bias, and hence increase in Vt, is created in NMOSFETs M
1
-
0
. . . M
1
-
7
, when node X is greater than ground, thus reducing the domino precharge node dip. Leakage is reduced when two off NMOSFET transistors are stacked in series. During evaluate stage, leakage through evaluate network
34
is reduced because NMOSFET M
5
is stacked when M
1
-
0
. . . M
1
-
7
, respectively. While circuit
30
is easy to implement, it suffers from a large static power dissipation through M
4
and M
5
during the evaluate phase.
Accordingly, there is a need for a better noise tolerant wide-fanin domino circuit technique.
SUMMARY
The invention involves a die having domino circuits. In some embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and at least one intermediate node. The domino stage has improved noise immunity and reduced leakage through reverse body biasing transistors in the evaluate network by raising voltage of the at least one intermediate node without static power consumption through the evaluate network.
In other embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and wherein the domino stage further includes a diode transistor having a gate and an additional terminal connected to the domino stage output node.
Still other embodiments are described and claimed.
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Hegde Rajamohana
Krishnamurthy Ram K.
Wang Lei
Aldous Alan K.
Cho James H.
Intel Corporation
Tokar Michael
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