Noise-tolerant dynamic circuits

Details Noise-tolerant dynamic circuits Noise-tolerant dynamic circuits

1997-01-31

1998-08-11

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326121, H03K 19096

Patent

active

057932280

ABSTRACT:
More noise immunity is added to the inputs of precharged dynamic circuits without changing the functional characteristics of the dynamic circuit. A precharged dynamic circuit has a plurality of inputs connected to respective n-type field effect transistors (NFETs) in a tree between a precharge node and circuit ground. A tree of p-type FETs (PFETs) is connected between each of the inputs and a supply voltage with the output of the circuit being connected to the PFET closest to the supply voltage. When the output turns high, the PFET closest to supply voltage is turned off, preventing the precharged node from being prematurely reset.

REFERENCES:
patent: 3671779 (1972-06-01), Draper et al.
patent: 4779013 (1988-10-01), Tanaka
patent: 4985644 (1991-01-01), Okihara et al.
patent: 5237213 (1993-08-01), Tanoi
patent: 5430335 (1995-07-01), Tanoi
patent: 5541880 (1996-07-01), Campardo et al.
patent: 5557223 (1996-09-01), Kuo

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