Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2008-08-05
2011-12-20
Tsai, Henry (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C713S400000
Reexamination Certificate
active
08082375
ABSTRACT:
This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line.
REFERENCES:
patent: 2002/0054684 (2002-05-01), Menzl
patent: 2002/0105842 (2002-08-01), Uchida et al.
patent: 2005/0245218 (2005-11-01), Jayaramen
patent: 2006/0277426 (2006-12-01), Lindorfer et al.
patent: 9-238150 (1997-09-01), None
patent: 9-238151 (1997-09-01), None
Goto Kensuke
Osawa Yasuo
Tokunaga Tetsuya
Yamagata Yoshiyuki
Morrison & Foerster / LLP
Nam Hyun
SANYO Semiconductor Co., Ltd.
Semiconductor Components Industries LLC
Tsai Henry
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