Noise tolerant code setting circuit

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding

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Details

326 9, 326 30, 327525, 327546, H03K 190948, H01H 3776

Patent

active

054464021

ABSTRACT:
In a code setting circuit wherein pad terminals are supplied with a voltage pulse to burn out corresponding thin-film resistors, first transistors of first conductivity type are adapted to be turned on in response to a turn-on pulse and second transistors of the first conductivity type are provided. The channel of each second transistor is connected in parallel with the channel of each first transistor between a voltage source and one of circuit nodes at which desired potentials are developed and a digital setting signal is generated corresponding thereto. Inverters are connected between the nodes and the gate terminals of the second transistors to keep the nodes at the desired potentials. Third transistors of second conductivity type are provided to prevent the voltage source from being coupled through the second transistors to the pad terminals. Blocking means are provided respectively corresponding to the third transistors and the pad terminals. Each blocking means is connected between the other end of the channel of the corresponding third transistor and the corresponding pad terminal for preventing a noise pulse generated when the voltage pulse is applied to the corresponding pad terminal from being applied to the corresponding third transistor.

REFERENCES:
patent: 4686384 (1987-08-01), Harvey et al.
patent: 4730129 (1988-03-01), Kunitoki et al.
patent: 5015889 (1991-05-01), Reay
patent: 5153458 (1992-10-01), Hinooka
patent: 5173616 (1992-12-01), Hinooka

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