Noise suppression method and circuits for sensitive circuits

Details Noise suppression method and circuits for sensitive circuits Noise suppression method and circuits for sensitive circuits

1996-06-18

1999-08-03

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 34, 326 24, H03K 1716

Patent

active

059330210

ABSTRACT:
Circuits and methods of suppressing noise on a signal line are disclosed. A noise suppression pull-down circuit is coupled to a signal line which couples the output element of a first logic element to the input terminal of a second logic element. When the first logic element drives a logic low onto the signal line, the noise suppression pull-down circuit is activated to provide a weak pull-down on the signal line. When the first logic element drives a logic high onto the signal line, the noise suppression pull-down circuit is deactivated to prevent interference with the first logic element.

REFERENCES:
patent: 3946251 (1976-03-01), Kawagoe
patent: 4498021 (1985-02-01), Uya
patent: 5027008 (1991-06-01), Runaldue
patent: 5166561 (1992-11-01), Okura
patent: 5218242 (1993-06-01), Imazu et al.

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