Noise suppression in memory device sensing

Details Noise suppression in memory device sensing Noise suppression in memory device sensing

2008-01-08

2008-01-08

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000, C365S185170

Reexamination Certificate

active

07317647

ABSTRACT:
NAND memory devices utilize sensing devices for sensing a programmed state of a nonvolatile memory cell or writing a data value to a nonvolatile memory cell. Latches in sensing devices are selectively coupled to a variable-potential node to receive a first potential to switch the latch, i.e., presetting, setting or resetting the latch. After switching, the variable-potential node may be set to an intermediate potential to increase noise immunity to the latch while holding the data value. In NAND sensing devices having a data latch and a cache latch, the variable-potential nodes of the data latch and the variable-potential nodes of the cache latch are coupled to separate ground control circuits. By independently varying the potentials applied to the variable-potential nodes of the data latch and cache latch, determined by whether the individual latch is switching or holding data, noise immunity in the data path is increased.

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