Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-18
2006-04-18
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S002000
Reexamination Certificate
active
07032195
ABSTRACT:
In a method of selecting a suitable noise suppression component, an input signal to a digital circuit including a transmitter IC, a noise suppression filter, a transmission line, and a receiver IC is expanded by Fourier expansion so as to express the input signal in terms of a series sum of sine waves. The Fourier-expanded input signal and the circuit constants of the digital circuit are used to calculate a signal on the input side of the receiver IC. Similar calculation is performed for all possible filters to assign scores for each of fundamental and harmonic components of the signal, while considering both the noise suppressing effect and the signal waveform quality. Total scores are calculated, and the filters are ranked from a high score to a low score.
REFERENCES:
patent: 6950997 (2005-09-01), Dickey et al.
patent: 2001/0048298 (2001-12-01), Doshita et al.
patent: 2005/0165879 (2005-07-01), Nikitin et al.
patent: 2001-265848 (2001-09-01), None
Official Communication dated Sep. 23, 2005 issued in the corresponding Chinese Application No. 2004/0007326.3 (with English translation).
Doshita Kazuyuki
Ueno Haruhiko
Garbowski Leigh M.
Keating & Bennett LLP
Murata Manufacturing Co. Ltd.
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