Noise reduction during simultaneous operation of a flash memory

Details Noise reduction during simultaneous operation of a flash memory Noise reduction during simultaneous operation of a flash memory

2000-02-04

2000-12-12

Dinh, Son T.

Static information storage and retrieval

Addressing

Plural blocks or banks

G11C 702

Patent

active

061607509

ABSTRACT:
A flash memory device (100) includes a first bank (194) and a second bank (196) of memory cells. Address logic (416, 418, 420, 422) is configured to access read data at a first location in the first bank according to first address data. The address logic is configured to substantially simultaneously access for writing a plurality of second locations in the second bank according to second address data. The address logic is configured to access the plurality of second locations by varying only a single bit of the second address data at a time. This reduces the total number of address signals changing during sector erase in the flash memory device, thereby reducing noise which previously impacted the sense margin and access time in the device.

REFERENCES:
patent: 5768205 (1998-06-01), Hashimoto et al.
patent: 5864505 (1999-01-01), Higuchi
patent: 5867430 (1999-02-01), Chen et al.
patent: 6021077 (2000-02-01), Nakaoka

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