Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1999-10-25
2004-11-09
Abdelmoniem, Elamin (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C345S473000, C345S443000, C365S227000
Reexamination Certificate
active
06816930
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a noise reducing method for a radio portable terminal, and, more particularly, to a noise reducing method for reducing noise generated by a central processing unit (CPU) in a radio portable terminal.
2. Description of the Related Art
Conventional measures against noise in a radio portable terminal include a scheme of stopping the operation of the CPU in the radio portable terminal at the time of receiving data and a scheme of shielding the CPU, an external memory and so forth. Recently, there has been a demand for an improvement on the processing performance of radio portable terminals, which has led to an increasing use of fast CPUs. It is not therefore a good idea to stop the operation of the CPU.
When the CPU in a radio portable terminal accesses an external memory, large noise is generated. To suppress noise by reducing the number of accesses to the external memory, the conventional radio portable terminals use an exclusive read only memory (ROM) or random access memory (RAM) incorporated in the CPU.
For example, Japanese Patent No. 2748773 (hereinafter called “first prior art”) discloses a method of reducing noise generated by the operation of a CPU used in a radio receiving circuit, thereby improving the sensitivity of the radio receiving circuit.
FIG. 7
presents a structural diagram of a conventional radio portable terminal which is disclosed in the first prior art. The radio portable terminal shown in
FIG. 7
comprises a microprocessor
300
which operates in a dual mode, an interface
205
, a user interface
117
, a mode switch
308
, a RAM
202
and a ROM
201
.
This dual-mode microprocessor
300
has a RAM
301
and ROM
302
as its internal memories. The ROM
302
may be a masked ROM or an erasable programmable ROM (EPROM). This dual-mode microprocessor
300
may further include an electrically erasable programmable ROM (EEPROM)
303
which can be used for permanent storage of a program or data.
The mode switch
308
is connected to first-mode and second-mode select terminals (not shown) via a plurality of conductors
309
. The user interface
117
is connected via a control input conductor
307
to the microprocessor
300
to provide the microprocessor
300
with predetermined information. Specifically, the control input conductor
307
provides means for starting the mode change (between the first mode and the second mode) in the dual-mode microprocessor
300
. The user interface
117
is connected to the microprocessor
300
by a plurality of data input lines
305
and a plurality of data output lines
306
.
It is understood from experiments that the level of noise generated in the dual-mode microprocessor
300
can be reduced considerably when the microprocessor
300
operates only in internal mode (the aforementioned first mode) where the individual internal memories
301
,
302
and
303
are mainly used, as compared with a case where the microprocessor
300
operates in external mode (the second mode) in which an external memory is used. In the first prior art, therefore, the dual-mode microprocessor
300
operates while being switched to a single-chip mode, i.e., the internal mode, or an extension mode, i.e., the external mode. Specifically, the basic operation is carried out in single-chip mode in which case noise to be generated by an operation to access an external device connected to the CPU or an external memory via an external bus is minimized. When the microprocessor
300
is operating in this single-chip mode, the ROM
201
and RAM
202
as external memories are inactive. Further, no signals are flowing through an external address bus
203
and a data bus
204
. The level of noise to be generated is reduced by setting those external memories and external buses inactive and optimizing the time for which the microprocessor
300
operates in single-chip mode.
To reduce the level of noise generated by the microprocessor
300
while the radio portable terminal is receiving radio data, the programs that are stored in the dual-mode microprocessor
300
should be categorized. More specifically, individual modules (routines) included in the programs are associated with the respective functions of the radio portable terminal by systematically analyzing the codes of each program. Based on those functions, the modules can be separated into two main categories.
The modules of the first category are associated with the functions that are susceptible to the influence of noise, e.g., the radio receiving function. The modules of the first category are executed inside the microprocessor
300
when it is operating in single-chip mode.
The modules of the second category are associated with the functions that are insusceptible to the influence of noise, such as the radio transmitting function, the function for changing the operation mode of the radio portable terminal and the function to communicated with a user. The modules of the second category operate in extension mode using the ROM
201
and RAM
202
as external memories, the external address bus
203
and the data bus
204
.
It is ideal to store all the modules of the first category in the internal ROM (EPROM)
302
, more desirably, into the internal EEPROM
303
of the microprocessor
300
. The EEPROM
303
may further retain data which varies only occasionally. To effectively use an additional memory which is provided by the internal RAM
301
, the modules of the first category are further separated into a main algorithm and sub algorithms.
The main algorithm of the first category consists of an active program which runs continuously. The sub algorithms are programs which are called as needed and frequently use the external address bus, and each sub algorithm is formed by, for example, a delay loop or a loop which monitors a change in the status of the input or the like. The software is designed in such a way that the main algorithm of the first category is permanently saved in the internal ROM
302
(EPROM) of the microprocessor
300
and the sub algorithms of the first category are stored first in the external memories
201
and
202
. Each sub algorithm is transferred to the internal RAM
301
every time it is called or only when its specific module is needed. Once the module of any sub algorithm is loaded into the internal RAM
301
, this sub algorithm is executed when the microprocessor
300
returns to the single-chip mode or the internal mode.
Unexamined Japanese Patent Publication (KOKAI) No. Hei 7-203510 (hereinafter called “second prior art”) discloses a method of reducing the frequency of the system reference clock when a radio portable terminal is used.
Another Unexamined Japanese Patent Publication (KOKAI) No. Hei 8-70258 (hereinafter called “third prior art”) discloses a method of changing the frequency of the reference clock in such a manner as to avoid interference between the frequency that is used in the transmission and reception operations of a radio portable terminal and the harmonics of the reference clock.
The aforementioned first prior art has the following problems.
The first problem is the necessity of an exclusive CPU. That is, because a RAM and ROM should be incorporated in a CPU in the first prior art, a conventional ordinary CPU cannot achieve the object.
The second problem lies in that the RAM should be of an exclusive type for the following reason. As a cache in a general-purpose CPU is capable of automatically caching a saved command or data, such a command or data in the incorporated cache is freely rewritten when an external memory is accessed. This leads to the necessity of an exclusive RAM which prevents automatic rewriting of the contents of the cache.
Another solution is to store a program (commands) or data in a non-cache area so that the program (commands) or data will not be cached. But, this scheme prevents the internal RAM from functioning as a cache in normal operation mode, the system's processing speed in normal operation mode is slowed.
The third problem is that the CPU
Abdelmoniem Elamin
Foley & Lardner
NEC Corporation
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