Noise insensitive high performance energy efficient push pull is

Details Noise insensitive high performance energy efficient push pull is Noise insensitive high performance energy efficient push pull is

1996-09-25

1998-06-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327208, 327218, H03K 3356

Patent

active

057677166

ABSTRACT:
An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase having an input connected to the output of the inverter and an output connected to the output of the slave latch. This push-pull circuit speeds the C-to-Q delay time of the circuit because there is only one gate delay to output using this circuit. The master and slave latches may employ N-type MOSFETS, CMOS transfer gates or tri-state inverters in the feedback path. The master latch may employ a double pass transistor logic input. The push-pull circuit may employ a tri-state invertor in place of the inverter and transmission gate.

REFERENCES:
patent: 4691122 (1987-09-01), Schnizlein et al.
patent: 5463340 (1995-10-01), Takabatake et al.
patent: 5497114 (1996-03-01), Shimozono et al.
patent: 5552738 (1996-09-01), Ko

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