Noise elimination circuit

Details Noise elimination circuit Noise elimination circuit

2007-02-20

2007-02-20

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S026000, C327S551000

Reexamination Certificate

active

10998838

ABSTRACT:
A noise elimination circuit sets a certain time period for eliminating noise occurring immediately after a change in the logic level of an input signal by a delay time of a first delay buffer. It also adjusts the timing of switching by delay times of second and third delay buffers. The noise elimination circuit thereby blocks the input signal for a certain period of time immediately after the change in the logic level of the input signal to keep a switching signal by a latch circuit or transmit only the same logic level as the input signal to an output.

REFERENCES:
patent: 4334157 (1982-06-01), Ferris
patent: 4760279 (1988-07-01), Saito et al.
patent: 5019724 (1991-05-01), McClure
patent: 06-216723 (1994-08-01), None
patent: 10-294652 (1998-11-01), None

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